[PATCH] D139679: [X86] Don't zero out %eax if both %al and %ah are used

[Bill Wendling via Phabricator via llvm-commits]

void added a comment.

In D139679#3986385 <https://reviews.llvm.org/D139679#3986385>, @pengfei wrote:

> In D139679#3985095 <https://reviews.llvm.org/D139679#3985095>, @nickdesaulniers wrote:
>
>>> The iterator over super and sub registers doesn't include both 8-bit registers in its list.
>>
>> This is the use of `sub_and_superregs_inclusive` in the caller `PEI::insertZeroCallUsedRegs()` that you're referring to? Does that need to be fixed? Is there another iterator that gives us both? Should there be?  Maybe @pengfei , @RKSimon , or @craig.topper knows?
>>
>> The generated `TargetRegisterClass` for `GR8RegClass` and `GRH8RegClass` BOTH have set `CoveredBySubRegs` to `false`.
>
> I didn't know `sub_and_superregs_inclusive`. But I think I figured it out with a small code https://godbolt.org/z/9q8j66sYr
> Unfortunately I cannot figure out how to succefully link it in CE. Here is the command I used locally `clang++ Regs.cpp -I llvm/include/ -std=c++17 -Ibuilds/include -lLLVMSupport -lLLVMCore -lLLVMMC -lLLVMMCDisassembler -lLLVMTarget -lLLVMX86Desc -lLLVMX86Disassembler -lLLVMX86Info -lLLVMBinaryFormat -Lbuilds/lib -fuse-ld=lld -lpthread -lz -lzstd -fno-rtti -ltinfo`.
> As you can see, when pass `AH` (2) to it, it returns `AH`, `AX`, `EAX` and `RAX`. But if we pass `AX` (3) to it, it returns `AL`, `AH`, `AX`, `EAX` and `RAX`. I think the API works as expected because `AL` is not sub of `AH` but sibling.

Thanks, @pengfei, that confirms what I suspected. Maybe there should be an "and siblings" iterator as well.


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https://reviews.llvm.org/D139679