[PATCH] D139550: [DAGCombine] Fix always true condition in combineShiftToMULH

Mon Dec 12 06:30:12 PST 2022

RKSimon added a comment.

In D139550#3988343 <https://reviews.llvm.org/D139550#3988343>, @jmmartinez wrote:

> Or you mean having a srl and a sra in the same test-case?

Yes this is the test case I think we need to ensure we have a test case that has different behaviour for the if statement - if you precommit that srl+sra test then and rebase this patch the test codegen should change to match.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139550/new/

https://reviews.llvm.org/D139550