[PATCH] D139753: [RISCV] Eanble the Machine Late Cleanup pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: reames, asb, luismarques, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson, qcolombet.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

Believe the bug has been fixed with D139169 <https://reviews.llvm.org/D139169>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139753

Files:
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/branch-relaxation.ll
  llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/stack-realignment.ll

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