[PATCH] D134423: [AMDGPU] Fix vgpr2sgpr copy analysis to check scalar operands of buffer instructions use scalar registers.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

I think the best quick fix would be something like this in legalizeOperands, not changing SIFixSGPRCopies:

  diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  index c14b8df1f390..b79d343e0ed5 100644
  --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  @@ -6005,6 +6005,12 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
     if (RsrcIdx != -1) {
       // We have an MUBUF instruction
  +    MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soffset);
  +    if (SOff->isReg() && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
  +      Register SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
  +      SOff->setReg(SGPR);
  +    }
  +
       MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
       unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
       if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),


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  https://reviews.llvm.org/D134423/new/

https://reviews.llvm.org/D134423