[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondops Extension

[Kautuk Consul via Phabricator via llvm-commits]

kconsul updated this revision to Diff 481600.
kconsul added a comment.

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <kconsul at ventanamicro.com>
Signed-off-by: Mikhail Gudim <mgudim at ventanamicro.com>

Changes since v2:

- Inserted a space before "(VT_MASKCN"
- Removed the xventanacondops-valid.s and xventanacondops-invalid.s
- Modified the code in RISCVTargetLowering::RISCVTargetLowering() so that the setOperationAction for ISD::SELECT is called only when xvenatancondops attribute is not set.
- Modified the xventanacondops.ll test-case to check till full asm.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139394/new/

https://reviews.llvm.org/D139394

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/test/CodeGen/RISCV/xventanacondops.ll

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