[PATCH] D139699: [RISCV][WIP] Add register class for instructions that ignore register groups

Wang Pengcheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 9 02:21:25 PST 2022


pcwang-thead created this revision.
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This new register class can contain all valid vector VTs but only
single vector register will be allocated to it.

This is a potential approach to model instructions that ignore LMUL
and vector register groups like vmv.s.x/vfmv.s.f and reductions
instructions.

The key point is how we handle reg-to-reg copies between this new
register class and other register classes. As what the diffs have
shown, there are a lot of redundant vmv1r.v instuctions which can
be eliminated.

I post this patch here to discuss if this approach is feasible.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139699

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

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