[PATCH] D139693: Adjust format

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 created this revision.
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XinWang10 requested review of this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139693

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20810,14 +20810,13 @@
       if (VT.getVectorNumElements() <= 2 || !VecIn2.getNode())
         return SDValue();
       assert(InVT2Size <= InVT1Size &&
-              "Second input is not going to be larger than the first one.");
+             "Second input is not going to be larger than the first one.");
 
       // VecIn1 is wider than the output, and we have another, possibly
       // smaller input. Pad the smaller input with undefs, shuffle at the
       // input vector width, and extract the output.
       // The shuffle type is different than VT, so check legality again.
-      if (LegalOperations &&
-          !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1))
+      if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1))
         return SDValue();
 
       // Legalizing INSERT_SUBVECTOR is tricky - you basically have to
@@ -20825,7 +20824,7 @@
       // illegal, don't even try.
       if (InVT1 != InVT2) {
         VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1,
-                              DAG.getUNDEF(InVT1), VecIn2, ZeroIdx);
+                             DAG.getUNDEF(InVT1), VecIn2, ZeroIdx);
       }
       ShuffleNumElems = InVT1Size / VTSize * NumElems;
     } else {


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