[PATCH] D139656: [RISCV] Build single element vector for start of reduction change

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

In D139656#3982876 <https://reviews.llvm.org/D139656#3982876>, @reames wrote:

> Talked to Craig because I hadn't followed his last comment.
>
> The issue that we have is that vmv.x.s is modeled badly.  We model it as if it had an LMUL8 variant, but if you read the actual instruction manual you'll see that it ignores register groups and only writes to a single register.  This isn't a correctness concern, but it does mean that this patch over constrains the register allocator (by using a lmul8 reg class), which could result in poor codegen.  This is only an issue for this call site as the previous callsite (earlier change in stack), already had this issue and was likely going to write to the full LMUL8 register group in the following instruction anyways.  The reduction instruction also only writes to a single vector register.

If I understand correctly, the concern is, though the vmv.s.x/vmv.s.f ignore LMUL and vector register groups, we will still allocate a register with LMUL>1 register class for them, which will result in bad register allocation. And this is same for the destination register of reduction instructions.
Hmmmm…so we may apply these optimizations only for LMUL<=1, or redesign the pseudos of vmv.s.x/vmv.s.f and reductions (sooner of later).


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