[PATCH] D139685: Expand usage of CreateBuildVecShuffle to make full use of vector ops

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 added a comment.

In D139685#3983239 <https://reviews.llvm.org/D139685#3983239>, @HaohaiWen wrote:

>> Now, when llc encounters the case that contains a lot of extract_vector_elt and a BUILD_VECTOR, it will replace these to vector_shuffle to decrease the size of code, the actions are done in createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle the case that the size of source vector reg is more than twice the dest size.
>
> Better to limit column width to 80.
>
> Now, when llc encounters the case that contains a lot of
> extract_vector_elt and a BUILD_VECTOR, it will replace these to
> vector_shuffle to decrease the size of code, the actions are done in
> createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle
> the case that the size of source vector reg is more than twice the dest
> size.

Got it.


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  https://reviews.llvm.org/D139685/new/

https://reviews.llvm.org/D139685