[PATCH] D139685: Expand usage of CreateBuildVecShuffle to make full use of vector ops

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 created this revision.
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Now, when llc encounters the case that contains a lot of extract_vector_elt and a BUILD_VECTOR, it will replace these to vector_shuffle to decrease the size of code, the actions are done in createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle the case that the size of source vector reg is more than twice the dest size.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139685

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/avg.ll
  llvm/test/CodeGen/X86/pr29112.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll

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