[PATCH] D139565: [IR] add new callbrpad instruction

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers added a comment.

In D139565#3982939 <https://reviews.llvm.org/D139565#3982939>, @efriedma wrote:

>> I'm not certain either; it looks like SelectionDAGISel::SelectAllBasicBlocks does a ReversePostOrderTraversal of the basic blocks of a function.
>
> The point of this digression is just that it might be more straightforward to avoid depending on anything in particular being present in the FunctionLoweringInfo .

So one idea/prototype I did have relied on basically reparsing the constraint string of the inline asm via `TargetLowering::ParseConstraints`, as is done for `SelectionDAGBuilder::visitInlineAsm` (but just for the outputs).  I guess it's a fair point that we might not yet have an entry for the `callbr` value in the `FunctionLoweringInfo` yet.  So perhaps I will have to parse the constraints in such a case, then use RegsForValue to define the initial virtual register. I believe then SelectionDAG will find+reuse that virtreg for the `callbr` when it is eventually encountered. I believe this is how SelectionDAGBuilder can define virtregs for values when the use is visited before the def.

>> Any thoughts on what this "token" should be? i.e. a new instruction, call to a new intrinsic, one entry phi with metadata, <other>?
>
> Intrinsic is hopefully sufficient here.  (One entry PHI is very fragile, new instruction is a lot of work to implement.)

SGTM.  Many intrinsics are categorized as "Code Generator Intrinsics" (https://llvm.org/docs/LangRef.html#code-generator-intrinsics) so they seem an appropriate tool here. Hopefully they don't live long enough to need any of the isEHPad pinning as is done in this commit.

(If folks have other feedback/ideas/compliments/insults, I'd be happy to hear them before embarking on the above plan; I'll summarize it in the RFC https://discourse.llvm.org/t/rfc-syncing-asm-goto-with-outputs-with-gcc/65453/5 too).


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