[PATCH] D139648: [RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2836
+  // need two instructions (to materialize constant and then insrt), so
+  // lmul2 vmv.v.i requires about the same work.
+  if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar)) {
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craig.topper wrote:
> This might not be strictly true on an architecture with data path width less than VLEN. If SEW fits within the datapath length, vmv.x.s could be done in less than cycles than an LMUL=1 vmv.v.i. And LMUL=2 vmv.v.i would be 4x or more cycles than than vmv.x.s in such an architecture.
> 
> But I'm not sure how big of an issue that is.
While I agree with you in principle, I think we can safely punt this to the future.  Our cost modeling for vector operations considers splats linear in LMUL.  When we change that, we can change this location as well.  


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  https://reviews.llvm.org/D139648/new/

https://reviews.llvm.org/D139648