[PATCH] D139616: [TableGen] Emit table mapping physical registers to base classes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Thanks, it's nice to finally move some of this stuff into tablegen. Can you add a test, or at least the AMDGPU sample usage?



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Comment at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:696
 
+  /// Return target defined base register class for a physical register.
+  virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const {
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Should elaborate on what base means here.


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Comment at: llvm/utils/TableGen/RegisterInfoEmitter.cpp:1629
+      std::vector<uint8_t> Mapping;
+      Mapping.resize(Regs.size() + 1, 0);
+      for (int RCIdx = BaseClasses.size() - 1; RCIdx >= 0; --RCIdx) {
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foad wrote:
> Why `+ 1`?
Can do this directly in constructor


Repository:
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  https://reviews.llvm.org/D139616/new/

https://reviews.llvm.org/D139616