[PATCH] D136722: [AArch64] Extending lowering of 'zext <Y x i8> %x to <Y x i8X>' to use tbl instructions

[NILANJANA BASU via Phabricator via llvm-commits]

nilanjana_basu marked an inline comment as done.
nilanjana_basu added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13774
+  unsigned ZExtFactor =
+      (cast<IntegerType>(DstTy->getElementType())->getBitWidth()) /
+      (cast<IntegerType>(SrcTy->getElementType())->getBitWidth());
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fhahn wrote:
> I *think* we could have something like `zext i8 to i33` and then the division will drop the remainder. Could you add a test to see if that's the case and make sure we don't perform an incorrect transformation? It should be fine to just ignore cases where there would be remainder.
I have also added testing for the Global-ISel path.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D136722