[PATCH] D139646: AMDGPU: Check if operand with vgpr RC contains reg when printing

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: piotr, dp, foad, Joe_Nash.
Herald added subscribers: kosarev, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
Herald added a project: All.
Petar.Avramovic requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Disassembler can successfully decode sgpr register when only vgpr
registers are valid for the operand (e.g. VReg_* and VISrc_* operands).
In InstPrinter, detect when operands register class (vgpr classes only)
does not contain register that is being printed. Does not result in an
error. Intended use is for disassembler testing.


https://reviews.llvm.org/D139646

Files:
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/test/MC/Disassembler/AMDGPU/decode-err.txt


Index: llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -21,14 +21,14 @@
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], /*invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 [0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c] # src0 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] # src0 sgpr0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b] # src2 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
 [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18] # src2 sgpr0
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -667,6 +667,20 @@
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegOperand(Op.getReg(), O, MRI);
+
+    // Check if non-vgpr register was used in vgpr operand.
+    // Intention: print disassembler message when invalid code is decoded,
+    // for example sgpr register encoded in VReg or VISrc(VReg or imm) operand.
+    if (MI->getOpcode() != AMDGPU::SI_ILLEGAL_COPY) {
+      const MCRegisterClass *RC = &MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
+      if (!RC->contains(Op.getReg())) {
+        StringRef RCName(MRI.getRegClassName(RC));
+        if (RCName.contains("VReg_")) {
+          O << "/*Invalid register, operand has \'" << RCName
+            << "\' register class*/";
+        }
+      }
+    }
   } else if (Op.isImm()) {
     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
     switch (OpTy) {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D139646.481334.patch
Type: text/x-patch
Size: 3162 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221208/1626a025/attachment.bin>