[PATCH] D133340: [PowerPC][GISel]select floating point constant from TOC

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp:250
+
+  // Address stored in the TOC entry. This is related to code model and ABI we
+  // are currently using. For now we only handle 64-bit Linux LE.
----------------
Minor wording suggestion.


================
Comment at: llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp:252
+  // are currently using. For now we only handle 64-bit Linux LE.
+  // PowerPC only support small, medium and large code model.
+  const CodeModel::Model CModel = TM.getCodeModel();
----------------
Minor wording suggestion.


================
Comment at: llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp:268
+        .addReg(PPC::X2);
+  } else {
+    Register HaAddrReg =
----------------
Since the large and medium code models looks like they differ from just the opcode, does it make sense to do something like this?
```
unsigned Opcode = 0;
if (CModel == CodeModel::Large)
  // For large code model, generate LDtocL(CPI, ADDIStocHA8(X2, CPI))
  Opcode = PPC::LDtocL;
else
  // For medium code model, generate ADDItocL(CPI, ADDIStocHA8(X2, CPI))
  Opcode = PPC::ADDItocL;

Register HaAddrReg =
        MRI.createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
BuildMI(*I.getParent(), I, DbgLoc, TII.get(PPC::ADDIStocHA8), HaAddrReg)
        .addReg(PPC::X2)
        .addConstantPoolIndex(CPI);

BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opcode), AddrReg)
          .addConstantPoolIndex(CPI)
          .addReg(HaAddrReg);
```


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D133340