[llvm] f4cc734 - [DAG] Teach isConstOrConstSplat about SPLAT_VECTORs
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 8 03:53:29 PST 2022
Author: David Green
Date: 2022-12-08T11:53:25Z
New Revision: f4cc734a330dabf9fdf44b92432b3a4a9f811b01
URL: https://github.com/llvm/llvm-project/commit/f4cc734a330dabf9fdf44b92432b3a4a9f811b01
DIFF: https://github.com/llvm/llvm-project/commit/f4cc734a330dabf9fdf44b92432b3a4a9f811b01.diff
LOG: [DAG] Teach isConstOrConstSplat about SPLAT_VECTORs
This teaches the DemandedElts version of isConstOrConstSplat about
SPLAT_VECTORS, in the same way as the non-DemandedElts version by
calling the demanded-bits version from the non-demanded-bits version.
Differential Revision: https://reviews.llvm.org/D128919
Added:
llvm/test/CodeGen/AArch64/sve-knownbits.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 86b38a523a0d1..cf3b80f5cfe28 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10961,6 +10961,16 @@ bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, bool AllowUndefs,
bool AllowTruncation) {
+ EVT VT = N.getValueType();
+ APInt DemandedElts = VT.isFixedLengthVector()
+ ? APInt::getAllOnes(VT.getVectorMinNumElements())
+ : APInt(1, 1);
+ return isConstOrConstSplat(N, DemandedElts, AllowUndefs, AllowTruncation);
+}
+
+ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
+ bool AllowUndefs,
+ bool AllowTruncation) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
return CN;
@@ -10976,36 +10986,13 @@ ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, bool AllowUndefs,
}
}
- if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
- BitVector UndefElements;
- ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
-
- // BuildVectors can truncate their operands. Ignore that case here unless
- // AllowTruncation is set.
- if (CN && (UndefElements.none() || AllowUndefs)) {
- EVT CVT = CN->getValueType(0);
- EVT NSVT = N.getValueType().getScalarType();
- assert(CVT.bitsGE(NSVT) && "Illegal build vector element extension");
- if (AllowTruncation || (CVT == NSVT))
- return CN;
- }
- }
-
- return nullptr;
-}
-
-ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
- bool AllowUndefs,
- bool AllowTruncation) {
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
- return CN;
-
if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
BitVector UndefElements;
ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
// BuildVectors can truncate their operands. Ignore that case here unless
// AllowTruncation is set.
+ // TODO: Look into whether we should allow UndefElements in non-DemandedElts
if (CN && (UndefElements.none() || AllowUndefs)) {
EVT CVT = CN->getValueType(0);
EVT NSVT = N.getValueType().getScalarType();
@@ -11019,21 +11006,11 @@ ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
}
ConstantFPSDNode *llvm::isConstOrConstSplatFP(SDValue N, bool AllowUndefs) {
- if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
- return CN;
-
- if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
- BitVector UndefElements;
- ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
- if (CN && (UndefElements.none() || AllowUndefs))
- return CN;
- }
-
- if (N.getOpcode() == ISD::SPLAT_VECTOR)
- if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
- return CN;
-
- return nullptr;
+ EVT VT = N.getValueType();
+ APInt DemandedElts = VT.isFixedLengthVector()
+ ? APInt::getAllOnes(VT.getVectorMinNumElements())
+ : APInt(1, 1);
+ return isConstOrConstSplatFP(N, DemandedElts, AllowUndefs);
}
ConstantFPSDNode *llvm::isConstOrConstSplatFP(SDValue N,
@@ -11046,10 +11023,15 @@ ConstantFPSDNode *llvm::isConstOrConstSplatFP(SDValue N,
BitVector UndefElements;
ConstantFPSDNode *CN =
BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
+ // TODO: Look into whether we should allow UndefElements in non-DemandedElts
if (CN && (UndefElements.none() || AllowUndefs))
return CN;
}
+ if (N.getOpcode() == ISD::SPLAT_VECTOR)
+ if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
+ return CN;
+
return nullptr;
}
diff --git a/llvm/test/CodeGen/AArch64/sve-knownbits.ll b/llvm/test/CodeGen/AArch64/sve-knownbits.ll
new file mode 100644
index 0000000000000..2346d65995470
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-knownbits.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 8 x i16> @test_knownzero(<vscale x 8 x i16> %x) {
+; CHECK-LABEL: test_knownzero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z0.h, #0 // =0x0
+; CHECK-NEXT: ret
+ %a1 = shl <vscale x 8 x i16> %x, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 8, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ %a2 = and <vscale x 8 x i16> %a1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 8, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
+ ret <vscale x 8 x i16> %a2
+}
+
+define <vscale x 4 x i32> @asrlsr(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: asrlsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr z1.d, z1.d, #15
+; CHECK-NEXT: lsr z0.d, z0.d, #15
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %x = ashr <vscale x 4 x i64> %va, %vb
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
index eb4825f6688f8..10dc4de292abd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
@@ -34,7 +34,7 @@ define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv1i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vnsra.wi v8, v8, 15
+; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -76,7 +76,7 @@ define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv2i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vnsra.wi v10, v8, 15
+; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
@@ -119,7 +119,7 @@ define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv4i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnsra.wi v12, v8, 15
+; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
@@ -162,7 +162,7 @@ define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv8i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vnsra.wi v16, v8, 15
+; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
@@ -203,7 +203,7 @@ define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv1i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vnsra.wi v8, v8, 15
+; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -245,7 +245,7 @@ define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv2i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vnsra.wi v10, v8, 15
+; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
@@ -288,7 +288,7 @@ define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv4i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnsra.wi v12, v8, 15
+; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
@@ -331,7 +331,7 @@ define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv8i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vnsra.wi v16, v8, 15
+; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
More information about the llvm-commits
mailing list