[PATCH] D136722: [AArch64] Extending lowering of 'zext <Y x i8> %x to <Y x i8X>' to use tbl instructions

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Thanks for the latest update! This looks good in general to me, with just one more inline comment about an edge case



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13774
+  unsigned ZExtFactor =
+      (cast<IntegerType>(DstTy->getElementType())->getBitWidth()) /
+      (cast<IntegerType>(SrcTy->getElementType())->getBitWidth());
----------------
I *think* we could have something like `zext i8 to i33` and then the division will drop the remainder. Could you add a test to see if that's the case and make sure we don't perform an incorrect transformation? It should be fine to just ignore cases where there would be remainder.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136722/new/

https://reviews.llvm.org/D136722