[PATCH] D139616: [TableGen] Emit table mapping physical registers to base classes

[Carl Ritson via Phabricator via llvm-commits]

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Allow targets to define a mapping from registers to register
classes such that each register has exactly one base class.
As registers may be in multiple register classes the base class
is determined by the container class with the lowest BaseClassOrder.

Only register classes with BaseClassOrder set are considered
when determining the base classes.  By default BaseClassOrder is
unset in RegisterClass so no code is generated unless a target
explicit defines one or more base register classes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139616

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/include/llvm/Target/Target.td
  llvm/utils/TableGen/CodeGenRegisters.h
  llvm/utils/TableGen/RegisterInfoEmitter.cpp

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