[llvm] 564e09c - [RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-07T20:14:22-08:00
New Revision: 564e09c77870425d852f583c5aeb4dec57846ed7

URL: https://github.com/llvm/llvm-project/commit/564e09c77870425d852f583c5aeb4dec57846ed7
DIFF: https://github.com/llvm/llvm-project/commit/564e09c77870425d852f583c5aeb4dec57846ed7.diff

LOG: [RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.

2048 requires an LUI and ADDI instruction due to ADDI using a
signed immediate. It can also be done with C.LI+C.SLLI for better
code size.

With Zbs we can use a single BSETI to have an instruction.

Reorder the checks so that BSETI is checked first, with an extra
qualification to prefer a single LUI or ADDI when possible. I'm
continuing to think about other ways to structure this code, but
this works for now.

Fixes PR59362.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
    llvm/test/CodeGen/RISCV/imm.ll
    llvm/test/MC/RISCV/rv32zbs-aliases-valid.s
    llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index d651848baf406..2188cad8eeb93 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -50,6 +50,13 @@ static void generateInstSeqImpl(int64_t Val,
                                 RISCVMatInt::InstSeq &Res) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
 
+  // Use BSETI for a single bit that can't be expressed by a single LUI or ADDI.
+  if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val) &&
+      (!isInt<32>(Val) || Val == 0x800)) {
+    Res.emplace_back(RISCV::BSETI, Log2_64(Val));
+    return;
+  }
+
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -73,12 +80,6 @@ static void generateInstSeqImpl(int64_t Val,
 
   assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
 
-  // Use BSETI for a single bit.
-  if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val)) {
-    Res.emplace_back(RISCV::BSETI, Log2_64(Val));
-    return;
-  }
-
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits

diff  --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 4e80038dabcad..721b7331f2fb6 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -2422,3 +2422,36 @@ define i64 @PR54812() {
 ; RV64IZBS-NEXT:    ret
   ret i64 -2158497792;
 }
+
+define signext i32 @pos_2048() nounwind {
+; RV32I-LABEL: pos_2048:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    slli a0, a0, 11
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: pos_2048:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, 1
+; RV64I-NEXT:    slli a0, a0, 11
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: pos_2048:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    li a0, 1
+; RV64IZBA-NEXT:    slli a0, a0, 11
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBB-LABEL: pos_2048:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 1
+; RV64IZBB-NEXT:    slli a0, a0, 11
+; RV64IZBB-NEXT:    ret
+;
+; RV64IZBS-LABEL: pos_2048:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    bseti a0, zero, 11
+; RV64IZBS-NEXT:    ret
+  ret i32 2048
+}
+

diff  --git a/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s b/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s
index acf6839743290..1d70d2f9e7e24 100644
--- a/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbs-aliases-valid.s
@@ -30,3 +30,7 @@ binv x5, x6, 8
 # CHECK-S-OBJ-NOALIAS: bexti t0, t1, 8
 # CHECK-S-OBJ: bexti t0, t1, 8
 bext x5, x6, 8
+
+# CHECK-S-OBJ-NOALIAS: bseti t2, zero, 11
+# CHECK-S-OBJ: bseti t2, zero, 11
+li x7, 2048

diff  --git a/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s b/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
index 9d67d2b798ce1..ee789363683dd 100644
--- a/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbs-aliases-valid.s
@@ -56,3 +56,7 @@ li x6, 9223354442718100411
 # CHECK-S-OBJ-NEXT: bseti t1, t1, 46
 # CHECK-S-OBJ-NEXT: bseti t1, t1, 63
 li x6, -9223301666034697285
+
+# CHECK-S-OBJ-NOALIAS: bseti t2, zero, 11
+# CHECK-S-OBJ: bseti t2, zero, 11
+li x7, 2048