[llvm] f2ffdbe - [RISCV] Add accessors to RISCVMatInt::Inst.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 7 19:02:33 PST 2022
Author: Craig Topper
Date: 2022-12-07T19:02:01-08:00
New Revision: f2ffdbeb9c2d9d4c5915df07b30e5933d63e8e9a
URL: https://github.com/llvm/llvm-project/commit/f2ffdbeb9c2d9d4c5915df07b30e5933d63e8e9a
DIFF: https://github.com/llvm/llvm-project/commit/f2ffdbeb9c2d9d4c5915df07b30e5933d63e8e9a.diff
LOG: [RISCV] Add accessors to RISCVMatInt::Inst.
Make fields private. This helps hide that the Imm field doesn't
store a full int64_t.
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index dc1047631af76..90d22a23ade60 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2331,22 +2331,22 @@ void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
emitToStreamer(Out,
- MCInstBuilder(Inst.Opc).addReg(DestReg).addImm(Inst.Imm));
+ MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addImm(Inst.getImm()));
break;
case RISCVMatInt::RegX0:
emitToStreamer(
- Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
+ Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
RISCV::X0));
break;
case RISCVMatInt::RegReg:
emitToStreamer(
- Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addReg(
+ Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addReg(
SrcReg));
break;
case RISCVMatInt::RegImm:
emitToStreamer(
- Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
- Inst.Imm));
+ Out, MCInstBuilder(Inst.getOpcode()).addReg(DestReg).addReg(SrcReg).addImm(
+ Inst.getImm()));
break;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 9e09396b251a9..d651848baf406 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -20,7 +20,7 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
for (auto Instr : Res) {
// Assume instructions that aren't listed aren't compressible.
bool Compressed = false;
- switch (Instr.Opc) {
+ switch (Instr.getOpcode()) {
case RISCV::SLLI:
case RISCV::SRLI:
Compressed = true;
@@ -28,7 +28,7 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
case RISCV::ADDI:
case RISCV::ADDIW:
case RISCV::LUI:
- Compressed = isInt<6>(Instr.Imm);
+ Compressed = isInt<6>(Instr.getImm());
break;
}
// Two RVC instructions take the same space as one RVI instruction, but
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index c330f5e161e3f..8d71e0a22350b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -25,14 +25,18 @@ enum OpndKind {
RegX0, // ADD_UW
};
-struct Inst {
+class Inst {
unsigned Opc;
int32_t Imm; // The largest value we need to store is 20 bits.
+public:
Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
assert(I == Imm && "truncated");
}
+ unsigned getOpcode() const { return Opc; }
+ int64_t getImm() const { return Imm; }
+
OpndKind getOpndKind() const;
};
using InstSeq = SmallVector<Inst, 8>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 274c94ab2947a..1680ee478dffe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -177,20 +177,20 @@ static SDNode *selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
SDNode *Result = nullptr;
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);
for (RISCVMatInt::Inst &Inst : Seq) {
- SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, VT);
+ SDValue SDImm = CurDAG->getTargetConstant(Inst.getImm(), DL, VT);
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
- Result = CurDAG->getMachineNode(Inst.Opc, DL, VT, SDImm);
+ Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SDImm);
break;
case RISCVMatInt::RegX0:
- Result = CurDAG->getMachineNode(Inst.Opc, DL, VT, SrcReg,
+ Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SrcReg,
CurDAG->getRegister(RISCV::X0, VT));
break;
case RISCVMatInt::RegReg:
- Result = CurDAG->getMachineNode(Inst.Opc, DL, VT, SrcReg, SrcReg);
+ Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SrcReg, SrcReg);
break;
case RISCVMatInt::RegImm:
- Result = CurDAG->getMachineNode(Inst.Opc, DL, VT, SrcReg, SDImm);
+ Result = CurDAG->getMachineNode(Inst.getOpcode(), DL, VT, SrcReg, SDImm);
break;
}
@@ -1935,9 +1935,9 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
// If the last instruction would be an ADDI, we can fold its immediate and
// emit the rest of the sequence as the base.
- if (Seq.back().Opc != RISCV::ADDI)
+ if (Seq.back().getOpcode() != RISCV::ADDI)
return false;
- Lo12 = Seq.back().Imm;
+ Lo12 = Seq.back().getImm();
// Drop the last instruction.
Seq.pop_back();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 23c1a8125e1c2..acee7a9947079 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -698,26 +698,26 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
for (RISCVMatInt::Inst &Inst : Seq) {
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
- BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
- .addImm(Inst.Imm)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
+ .addImm(Inst.getImm())
.setMIFlag(Flag);
break;
case RISCVMatInt::RegX0:
- BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, RegState::Kill)
.addReg(RISCV::X0)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegReg:
- BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, RegState::Kill)
.addReg(SrcReg, RegState::Kill)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegImm:
- BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
+ BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, RegState::Kill)
- .addImm(Inst.Imm)
+ .addImm(Inst.getImm())
.setMIFlag(Flag);
break;
}
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