[PATCH] D139565: [IR] add new callbrpad instruction

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers added a comment.

In D139565#3979605 <https://reviews.llvm.org/D139565#3979605>, @nickdesaulniers wrote:

> In D139565#3979289 <https://reviews.llvm.org/D139565#3979289>, @efriedma wrote:
>
>> It's not clear to me an IR instruction is necessary.  I mean, I understand why you want a callbrpad-equivalent MachineInstr: the only existing infrastructure for jumping out of the middle of a block is the exception-handling infrastructure, so you want to handle callbr in a similar way.  I guess if you have a MachineInstr, but you don't have an IR instruction, doing the translation would involve SSA construction in isel, which is maybe a bit awkward.  But I'm not sure that's sufficient reason to introduce an IR instruction.  At the IR level, callbr is a terminator, and we produce the same value along all edges, so IR transforms don't benefit from distinguishing between direct and indirect edges.
>
> Consider the following control flow pattern psuedocode, without `callbrpad`.
>
>     %0 = callbr i32 ... to %direct [%indirect]
>   direct:
>     br label %direct_out
>   direct_out:
>     ret i32 %0
>   indirect:
>     br label %indirect_out
>   indirect_out:
>     ret i32 %0
>
> Where would you insert the potentially-necessary COPYs?  Which MBBs would you mark as having physreg liveins?  SelectionDAG thinks the value of the callbr is the first virtreg COPY after the INLINEASM_BR, which is incorrect for output branches. SelectionDAG has a 1:1 mapping of Value* to virtual register (`FuncInfo.ValueMap` used in this patch).  @jyknight  suggested it might be nice to have distinct SSA values for each indirect edge.

To expand on this; we might like to conceptually have one value `%0` in llvm ir, but in MIR, we'd need either a distinct virtreg per edge (or multiple defs of the same virt reg, which I _think_ MIR might actually support).


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