[PATCH] D133768: [DAGCombine] Do not fold SRA/SRL of MUL into MULH when MUL's LSB are used, and MUL_LOHI is available

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9249
+  auto UserOfLowerBits = [NarrowVTSize](SDNode *U) {
+    if (U->getOpcode() != ISD::SRL || U->getOpcode() != ISD::SRA) {
+      return true;
----------------
RKSimon wrote:
> jmmartinez wrote:
> > RKSimon wrote:
> > > @jmmartinez I'm getting static analysis warnings that this is always true - should this be:
> > > ```
> > > if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
> > > ```
> > Well spotted! I'll submit a fix for it. BTW what are you using for static analysis?
> Cheers - VisualAssist 'code inspection' caught this one
Sorry, amazingly its Intellisense that caught it - they get listed in the same window


Repository:
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  https://reviews.llvm.org/D133768/new/

https://reviews.llvm.org/D133768