[PATCH] D139394: [RISCV] Add support for RISCV XVentanaCondops Extension
Kautuk Consul via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 7 04:17:54 PST 2022
kconsul updated this revision to Diff 480849.
kconsul added a comment.
[RISCV] Add support for RISCV XVentanaCondops Extension
This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.
The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf
Signed-off-by: Kautuk Consul <kconsul at ventanamicro.com>
Signed-off-by: Mikhail Gudim <mgudim at ventanamicro.com>
Changes since v1:
- Rebased on the main branch.
- Ported my MASKC/MASKCN changes to VT_MASKC/VT_MASKCN as per Philip Reames' patch which added assembler support for the vt.maskc/vt.maskcn instructions.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139394/new/
https://reviews.llvm.org/D139394
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/test/CodeGen/RISCV/xventanacondops.ll
llvm/test/MC/RISCV/rv64xventanacondops-invalid.s
llvm/test/MC/RISCV/rv64xventanacondops-valid.s
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