[PATCH] D139504: [RISCV] Replace uses of hasStdExtC with COrZca.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 21:22:13 PST 2022
craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, VincentWu, reames, jrtc27.
Herald added subscribers: sunshaoce, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
Except MakeCompressible which will need more work.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D139504
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/test/CodeGen/RISCV/add-before-shl.ll
Index: llvm/test/CodeGen/RISCV/add-before-shl.ll
===================================================================
--- llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -7,6 +7,10 @@
; RUN: < %s | FileCheck -check-prefixes=RV32C %s
; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
; RUN: < %s | FileCheck -check-prefixes=RV64C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN: < %s | FileCheck -check-prefixes=RV32C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca -verify-machineinstrs --riscv-no-aliases \
+; RUN: < %s | FileCheck -check-prefixes=RV64C %s
; These test that constant adds are not moved after shifts by DAGCombine,
; if the constant is cheaper to materialise before it has been shifted.
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -562,7 +562,7 @@
unsigned
RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
- return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
+ return MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 1 : 0;
}
// Add two address hints to improve chances of being able to use a compressed
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -332,6 +332,7 @@
const RISCVInstrInfo &TII = *STI.getInstrInfo();
// This optimization only makes sense if compressed instructions are emitted.
+ // FIXME: Support Zca, Zcf, Zcd granularity.
if (!STI.hasStdExtC())
return false;
Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1058,7 +1058,7 @@
if (MI.isConditionalBranch())
FnSize += TII.getInstSizeInBytes(MI);
if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
- if (MF.getSubtarget<RISCVSubtarget>().hasStdExtC())
+ if (false && MF.getSubtarget<RISCVSubtarget>().hasStdExtC())
FnSize += 2 + 8 + 2 + 2;
else
FnSize += 4 + 8 + 4 + 4;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -366,7 +366,8 @@
int getIntMatCost(const APInt &Val, unsigned Size,
const FeatureBitset &ActiveFeatures, bool CompressionCost) {
bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
- bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
+ bool HasRVC = CompressionCost && (ActiveFeatures[RISCV::FeatureStdExtC] ||
+ ActiveFeatures[RISCV::FeatureExtZca]);
int PlatRegSize = IsRV64 ? 64 : 32;
// Split the constant into platform register sized chunks, and calculate cost
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