[PATCH] D139391: [RISCV] Codegen support for Zfhmin.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:288
+      const MachineFunction *MF = MBB.getParent();
+      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+      MCRegister F32DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
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I think you can use `const TargetRegisterInfo *TRI = STI.getRegisterInfo()`


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:289
+      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+      MCRegister F32DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
+                                                      &RISCV::FPR32RegClass);
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If we assigned over DstReg and SrcReg here and did `Opc = FSGNJ_S` and `IsScalableVector = false`, would the common code at the end still work?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139391/new/

https://reviews.llvm.org/D139391