[llvm] d249152 - [RISCV] Return InstSeq from generateInstSeqImpl instead of using an output parameter. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 14:57:52 PST 2022
Author: Craig Topper
Date: 2022-12-06T14:57:27-08:00
New Revision: d24915207c631b7cf637081f333b41bc5159c700
URL: https://github.com/llvm/llvm-project/commit/d24915207c631b7cf637081f333b41bc5159c700
DIFF: https://github.com/llvm/llvm-project/commit/d24915207c631b7cf637081f333b41bc5159c700.diff
LOG: [RISCV] Return InstSeq from generateInstSeqImpl instead of using an output parameter. NFC
We should be able to rely on RVO here.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 71855b546be4..6a1a6df14f47 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -45,9 +45,9 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
}
// Recursively generate a sequence for materializing an integer.
-static void generateInstSeqImpl(int64_t Val,
- const FeatureBitset &ActiveFeatures,
- RISCVMatInt::InstSeq &Res) {
+static RISCVMatInt::InstSeq
+generateInstSeqImpl(int64_t Val, const FeatureBitset &ActiveFeatures) {
+ RISCVMatInt::InstSeq Res;
bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
if (isInt<32>(Val)) {
@@ -68,7 +68,7 @@ static void generateInstSeqImpl(int64_t Val,
unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
Res.emplace_back(AddiOpc, Lo12);
}
- return;
+ return Res;
}
assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
@@ -76,7 +76,7 @@ static void generateInstSeqImpl(int64_t Val,
// Use BSETI for a single bit.
if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val)) {
Res.emplace_back(RISCV::BSETI, Log2_64(Val));
- return;
+ return Res;
}
// In the worst case, for a full 64-bit constant, a sequence of 8 instructions
@@ -140,7 +140,7 @@ static void generateInstSeqImpl(int64_t Val,
}
}
- generateInstSeqImpl(Val, ActiveFeatures, Res);
+ Res = generateInstSeqImpl(Val, ActiveFeatures);
// Skip shift if we were able to use LUI directly.
if (ShiftAmount) {
@@ -150,6 +150,8 @@ static void generateInstSeqImpl(int64_t Val,
if (Lo12)
Res.emplace_back(RISCV::ADDI, Lo12);
+
+ return Res;
}
static unsigned extractRotateInfo(int64_t Val) {
@@ -172,8 +174,7 @@ static unsigned extractRotateInfo(int64_t Val) {
namespace llvm::RISCVMatInt {
InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
- RISCVMatInt::InstSeq Res;
- generateInstSeqImpl(Val, ActiveFeatures, Res);
+ RISCVMatInt::InstSeq Res = generateInstSeqImpl(Val, ActiveFeatures);
// If the low 12 bits are non-zero, the first expansion may end with an ADDI
// or ADDIW. If there are trailing zeros, try generating a sign extended
@@ -187,8 +188,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
// code.
bool IsShiftedCompressible =
isInt<6>(ShiftedVal) && !ActiveFeatures[RISCV::TuneLUIADDIFusion];
- RISCVMatInt::InstSeq TmpSeq;
- generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(ShiftedVal, ActiveFeatures);
TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
// Keep the new sequence if it is an improvement.
@@ -203,36 +203,37 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
"Expected RV32 to only need 2 instructions");
unsigned LeadingZeros = countLeadingZeros((uint64_t)Val);
uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
- // Fill in the bits that will be shifted out with 1s. An example where this
- // helps is trailing one masks with 32 or more ones. This will generate
- // ADDI -1 and an SRLI.
- ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
- RISCVMatInt::InstSeq TmpSeq;
- generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
- TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
+ {
+ // Fill in the bits that will be shifted out with 1s. An example where
+ // this helps is trailing one masks with 32 or more ones. This will
+ // generate ADDI -1 and an SRLI.
+ ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
+ auto TmpSeq = generateInstSeqImpl(ShiftedVal, ActiveFeatures);
+ TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
- // Keep the new sequence if it is an improvement.
- if (TmpSeq.size() < Res.size())
- Res = TmpSeq;
+ // Keep the new sequence if it is an improvement.
+ if (TmpSeq.size() < Res.size())
+ Res = TmpSeq;
+ }
- // Some cases can benefit from filling the lower bits with zeros instead.
- ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
- TmpSeq.clear();
- generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
- TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
+ {
+ // Some cases can benefit from filling the lower bits with zeros instead.
+ ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
+ auto TmpSeq = generateInstSeqImpl(ShiftedVal, ActiveFeatures);
+ TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
- // Keep the new sequence if it is an improvement.
- if (TmpSeq.size() < Res.size())
- Res = TmpSeq;
+ // Keep the new sequence if it is an improvement.
+ if (TmpSeq.size() < Res.size())
+ Res = TmpSeq;
+ }
// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
// the end of the sequence.
if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
// Try replacing upper bits with 1.
uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
- TmpSeq.clear();
- generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(LeadingOnesVal, ActiveFeatures);
TmpSeq.emplace_back(RISCV::ADD_UW, 0);
// Keep the new sequence if it is an improvement.
@@ -262,8 +263,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
NewVal = Val & ~0x80000000ll;
}
if (isInt<32>(NewVal)) {
- RISCVMatInt::InstSeq TmpSeq;
- generateInstSeqImpl(NewVal, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(NewVal, ActiveFeatures);
TmpSeq.emplace_back(Opc, 31);
if (TmpSeq.size() < Res.size())
Res = TmpSeq;
@@ -275,8 +275,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
int32_t Lo = Lo_32(Val);
uint32_t Hi = Hi_32(Val);
Opc = 0;
- RISCVMatInt::InstSeq TmpSeq;
- generateInstSeqImpl(Lo, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(Lo, ActiveFeatures);
// Check if it is profitable to use BCLRI/BSETI.
if (Lo > 0 && TmpSeq.size() + countPopulation(Hi) < Res.size()) {
Opc = RISCV::BSETI;
@@ -302,7 +301,6 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
"Expected RV32 to only need 2 instructions");
int64_t Div = 0;
unsigned Opc = 0;
- RISCVMatInt::InstSeq TmpSeq;
// Select the opcode and divisor.
if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
Div = 3;
@@ -316,7 +314,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
}
// Build the new instruction sequence.
if (Div > 0) {
- generateInstSeqImpl(Val / Div, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(Val / Div, ActiveFeatures);
TmpSeq.emplace_back(Opc, 0);
if (TmpSeq.size() < Res.size())
Res = TmpSeq;
@@ -341,8 +339,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
// already been processed to LUI+SH*ADD by previous optimization.
assert(Lo12 != 0 &&
"unexpected instruction sequence for immediate materialisation");
- assert(TmpSeq.empty() && "Expected empty TmpSeq");
- generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq);
+ auto TmpSeq = generateInstSeqImpl(Hi52 / Div, ActiveFeatures);
TmpSeq.emplace_back(Opc, 0);
TmpSeq.emplace_back(RISCV::ADDI, Lo12);
if (TmpSeq.size() < Res.size())
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