[PATCH] D138521: [X86] Support ANDNP combine through broadcast instructions with scalar input

[Evgenii Kudriashov via Phabricator via llvm-commits]

e-kud added a comment.

In D138521#3974292 <https://reviews.llvm.org/D138521#3974292>, @RKSimon wrote:

> Do we have any 256/512 bit test coverage?

Unfortunately, no. I only tested locally with 256 bits.

I found out that the generic approach has a problem. If we have a 256 or 512 bit vector, then we can't generate `ANDNP` with SSE because there is no type for 256 bits. But after type-legalizer we have several `ISD::AND` that can be combined into `ANDNP`.
It works with `BROADCAST/PSHUFD` approach but performing the generic-combine before type-legalization prevents it.

I think about `and (shuffle(not)) -> and(not(shuffle))` reordering before type-legalization and then after legalization we combine them into `ANDNP`. However I'm not sure about such two-step combine. What do you think?


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