[PATCH] D139169: [RISCV][WIP] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/minor comment.



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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:440
 
-  auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());
-  if (ZvlssegInfo) {
-    MachineBasicBlock &MBB = *MI.getParent();
-    Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-    BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
-    uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
-    if (ShiftAmount != 0)
-      BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
-          .addReg(VL)
-          .addImm(ShiftAmount);
-    // The last argument of pseudo spilling opcode for zvlsseg is the length of
-    // one element of zvlsseg types. For example, for vint32m2x2_t, it will be
-    // the length of vint32m2_t.
-    MI.getOperand(FIOperandNum + 1).ChangeToRegister(VL, /*isDef=*/false);
+  switch (MI.getOpcode()) {
+  case RISCV::PseudoVSPILL2_M1:
----------------
Can you add a comment above this?  Something along the lines of:

Handle spill/fill of synthetic register classes for segment operations to ensure correctness in the edge case one gets spilled.  There are many possible optimizations here, but given the extreme rarity of such spills, we prefer simplicity of implementation for now.  




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https://reviews.llvm.org/D139169