[llvm] ee31a4a - [ARM] IselLowering unsigned overflow to crash using APInt in PerformSHLSimplify

[Peter Rong via llvm-commits]

Author: Peter Rong
Date: 2022-12-06T09:58:27-08:00
New Revision: ee31a4a7029f2f6fda5f416e7eb67ca3907d9e36

URL: https://github.com/llvm/llvm-project/commit/ee31a4a7029f2f6fda5f416e7eb67ca3907d9e36
DIFF: https://github.com/llvm/llvm-project/commit/ee31a4a7029f2f6fda5f416e7eb67ca3907d9e36.diff

LOG: [ARM] IselLowering unsigned overflow to crash using APInt in PerformSHLSimplify

This diff fixes issue https://github.com/llvm/llvm-project/issues/59317

We should check if bitwidth is lower than the shift amount before we subtract them to avoid unsigned overflow.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D139238

Added: 
    llvm/test/CodeGen/ARM/pr59317.ll

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c76b2bac718d2..a27afc5723da3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13773,10 +13773,13 @@ static SDValue PerformSHLSimplify(SDNode *N,
 
   APInt C2Int = C2->getAPIntValue();
   APInt C1Int = C1ShlC2->getAPIntValue();
+  unsigned C2Width = C2Int.getBitWidth();
+  if (C2Int.uge(C2Width))
+    return SDValue();
+  uint64_t C2Value = C2Int.getZExtValue();
 
   // Check that performing a lshr will not lose any information.
-  APInt Mask = APInt::getHighBitsSet(C2Int.getBitWidth(),
-                                     C2Int.getBitWidth() - C2->getZExtValue());
+  APInt Mask = APInt::getHighBitsSet(C2Width, C2Width - C2Value);
   if ((C1Int & Mask) != C1Int)
     return SDValue();
 

diff  --git a/llvm/test/CodeGen/ARM/pr59317.ll b/llvm/test/CodeGen/ARM/pr59317.ll
new file mode 100644
index 0000000000000..ebe80b3899b3f
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/pr59317.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm %s -o - | FileCheck --check-prefix=arm %s
+; RUN: llc -mtriple=armeb %s -o - | FileCheck --check-prefix=armeb %s
+
+define i1 @pr59317(i16 %F) {
+; arm-LABEL: pr59317:
+; arm:       @ %bb.0: @ %BB
+; arm-NEXT:    sub sp, sp, #8
+; arm-NEXT:    mov r0, #0
+; arm-NEXT:    add sp, sp, #8
+; arm-NEXT:    mov pc, lr
+;
+; armeb-LABEL: pr59317:
+; armeb:       @ %bb.0: @ %BB
+; armeb-NEXT:    sub sp, sp, #8
+; armeb-NEXT:    mov r0, #0
+; armeb-NEXT:    add sp, sp, #8
+; armeb-NEXT:    mov pc, lr
+BB:
+  %E = extractelement <1 x i16> <i16 -1>, i16 %F
+  %RP = alloca i64, align 8
+  %B = shl i16 %E, %E
+  %C1 = icmp ugt i16 %B, %F
+  ret i1 %C1
+}