[llvm] ce66f4d - [RISCV] Restrict when RISCVMatInt will retry SLLI as a last step. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-06T09:25:20-08:00
New Revision: ce66f4d0a6e0f5e756fc06992bb143d7bf6def66

URL: https://github.com/llvm/llvm-project/commit/ce66f4d0a6e0f5e756fc06992bb143d7bf6def66
DIFF: https://github.com/llvm/llvm-project/commit/ce66f4d0a6e0f5e756fc06992bb143d7bf6def66.diff

LOG: [RISCV] Restrict when RISCVMatInt will retry SLLI as a last step. NFC

The main algorithm will already end with a SLLI when there are 12
or more trailing zeros. We only need to retry when there are less
than 12 trailing zeros since the main algorithm will pick an ADDI
or ADDIW at the end for those cases.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index dc281778f061..f4e8a98b5937 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -175,9 +175,10 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   RISCVMatInt::InstSeq Res;
   generateInstSeqImpl(Val, ActiveFeatures, Res);
 
-  // If there are trailing zeros, try generating a sign extended constant with
-  // no trailing zeros and use a final SLLI to restore them.
-  if ((Val & 1) == 0 && Res.size() > 2) {
+  // If the low 12 bits are non-zero, the first expansion may end with an ADDI
+  // or ADDIW. If there are trailing zeros, try generating a sign extended
+  // constant with no trailing zeros and use a final SLLI to restore them.
+  if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() > 2) {
     unsigned TrailingZeros = countTrailingZeros((uint64_t)Val);
     int64_t ShiftedVal = Val >> TrailingZeros;
     RISCVMatInt::InstSeq TmpSeq;