[PATCH] D138186: InstCombine: Simplify vector load based on demanded elements

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 6 09:24:24 PST 2022


lebedev.ri added a comment.

In D138186#3973184 <https://reviews.llvm.org/D138186#3973184>, @nhaehnle wrote:

> In D138186#3970779 <https://reviews.llvm.org/D138186#3970779>, @arsenm wrote:
>
>> In D138186#3969988 <https://reviews.llvm.org/D138186#3969988>, @ruiling wrote:
>>
>>> I think the best solution for the motivating problem is in the backend, where the load instructions have reached its final form, thus could help more cases. A load in LLVM IR is still subject to either split or combine.
>>
>> I think the opposite. The backend load passes have to deal with way more patterns and addressing modes
>
> It could be done in the LLVM IR part of the code generation pipeline?

Don't we already do that in VectorCombine?


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