[llvm] 772c2f4 - [AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 08:36:42 PST 2022
Author: Sanjay Patel
Date: 2022-12-06T11:34:48-05:00
New Revision: 772c2f461b942032df8426a49077c37066783a68
URL: https://github.com/llvm/llvm-project/commit/772c2f461b942032df8426a49077c37066783a68
DIFF: https://github.com/llvm/llvm-project/commit/772c2f461b942032df8426a49077c37066783a68.diff
LOG: [AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
Added:
llvm/test/CodeGen/AArch64/signbit-test.ll
llvm/test/CodeGen/RISCV/signbit-test.ll
llvm/test/CodeGen/X86/signbit-test.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/signbit-test.ll b/llvm/test/CodeGen/AArch64/signbit-test.ll
new file mode 100644
index 0000000000000..624027b88ab66
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/signbit-test.ll
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x80000000
+; CHECK-NEXT: csel x0, x8, x0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x80000000
+; CHECK-NEXT: csel x0, x8, x0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x8000
+; CHECK-NEXT: csel x0, x8, x0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x8000
+; CHECK-NEXT: csel x0, x8, x0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x80
+; CHECK-NEXT: csel x0, x8, x0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 128
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst x0, #0x80
+; CHECK-NEXT: csel x0, x8, x0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i64 %x, 128
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i32_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x8000
+; CHECK-NEXT: csel w0, w8, w0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i32_i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x8000
+; CHECK-NEXT: csel w0, w8, w0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i32_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x80
+; CHECK-NEXT: csel w0, w8, w0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i32 %x, 128
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i32_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x80
+; CHECK-NEXT: csel w0, w8, w0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i32 %x, 128
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i16_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x80
+; CHECK-NEXT: csel w0, w8, w0, eq
+; CHECK-NEXT: ret
+entry:
+ %a = and i16 %x, 128
+ %r = icmp eq i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i16_i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x80
+; CHECK-NEXT: csel w0, w8, w0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i16 %x, 128
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i16_i7:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: tst w0, #0x40
+; CHECK-NEXT: csel w0, w8, w0, ne
+; CHECK-NEXT: ret
+entry:
+ %a = and i16 %x, 64
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
diff --git a/llvm/test/CodeGen/RISCV/signbit-test.ll b/llvm/test/CodeGen/RISCV/signbit-test.ll
new file mode 100644
index 0000000000000..69a9026d9af9e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/signbit-test.ll
@@ -0,0 +1,384 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s
+
+define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i64_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: bltz a0, .LBB0_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB0_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i64_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 32
+; RV64-NEXT: bltz a1, .LBB0_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB0_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
+; RV32-LABEL: test_set_mask_i64_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: bgez a0, .LBB1_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB1_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i64_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 32
+; RV64-NEXT: bgez a1, .LBB1_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB1_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i64_i16:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: slli a2, a0, 16
+; RV32-NEXT: bltz a2, .LBB2_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB2_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i64_i16:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 48
+; RV64-NEXT: bltz a1, .LBB2_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB2_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
+; RV32-LABEL: test_set_mask_i64_i16:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: slli a2, a0, 16
+; RV32-NEXT: bgez a2, .LBB3_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB3_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i64_i16:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 48
+; RV64-NEXT: bgez a1, .LBB3_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB3_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i64_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a2, a0, 128
+; RV32-NEXT: bnez a2, .LBB4_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB4_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i64_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: bnez a1, .LBB4_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB4_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 128
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
+; RV32-LABEL: test_set_mask_i64_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a2, a0, 128
+; RV32-NEXT: beqz a2, .LBB5_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB5_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i64_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: beqz a1, .LBB5_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB5_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i64 %x, 128
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i32_i16:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: slli a1, a0, 16
+; RV32-NEXT: bltz a1, .LBB6_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB6_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i32_i16:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 48
+; RV64-NEXT: bltz a1, .LBB6_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB6_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
+; RV32-LABEL: test_set_mask_i32_i16:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: slli a1, a0, 16
+; RV32-NEXT: bgez a1, .LBB7_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB7_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i32_i16:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: slli a1, a0, 48
+; RV64-NEXT: bgez a1, .LBB7_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB7_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i32_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a1, a0, 128
+; RV32-NEXT: bnez a1, .LBB8_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB8_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i32_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: bnez a1, .LBB8_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB8_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i32 %x, 128
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
+; RV32-LABEL: test_set_mask_i32_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a1, a0, 128
+; RV32-NEXT: beqz a1, .LBB9_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB9_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i32_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: beqz a1, .LBB9_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB9_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i32 %x, 128
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
+; RV32-LABEL: test_clear_mask_i16_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a1, a0, 128
+; RV32-NEXT: bnez a1, .LBB10_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB10_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_clear_mask_i16_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: bnez a1, .LBB10_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB10_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i16 %x, 128
+ %r = icmp eq i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
+; RV32-LABEL: test_set_mask_i16_i8:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a1, a0, 128
+; RV32-NEXT: beqz a1, .LBB11_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB11_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i16_i8:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 128
+; RV64-NEXT: beqz a1, .LBB11_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB11_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i16 %x, 128
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
+; RV32-LABEL: test_set_mask_i16_i7:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: andi a1, a0, 64
+; RV32-NEXT: beqz a1, .LBB12_2
+; RV32-NEXT: # %bb.1: # %t
+; RV32-NEXT: li a0, 42
+; RV32-NEXT: .LBB12_2: # %f
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_set_mask_i16_i7:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: andi a1, a0, 64
+; RV64-NEXT: beqz a1, .LBB12_2
+; RV64-NEXT: # %bb.1: # %t
+; RV64-NEXT: li a0, 42
+; RV64-NEXT: .LBB12_2: # %f
+; RV64-NEXT: ret
+entry:
+ %a = and i16 %x, 64
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
diff --git a/llvm/test/CodeGen/X86/signbit-test.ll b/llvm/test/CodeGen/X86/signbit-test.ll
new file mode 100644
index 0000000000000..eca3494eb5ccb
--- /dev/null
+++ b/llvm/test/CodeGen/X86/signbit-test.ll
@@ -0,0 +1,278 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testl $-2147483648, %eax # imm = 0x80000000
+; CHECK-NEXT: jne .LBB0_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB0_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testl $-2147483648, %eax # imm = 0x80000000
+; CHECK-NEXT: je .LBB1_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB1_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 2147483648
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testl $32768, %eax # imm = 0x8000
+; CHECK-NEXT: jne .LBB2_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB2_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testl $32768, %eax # imm = 0x8000
+; CHECK-NEXT: je .LBB3_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB3_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 32768
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i64_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: jne .LBB4_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB4_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 128
+ %r = icmp eq i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i64_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: je .LBB5_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB5_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i64 %x, 128
+ %r = icmp ne i64 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i64 [ %x, %entry], [ 42, %t]
+ ret i64 %ret
+}
+
+define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i32_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testl $32768, %edi # imm = 0x8000
+; CHECK-NEXT: jne .LBB6_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB6_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i32_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testl $32768, %edi # imm = 0x8000
+; CHECK-NEXT: je .LBB7_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB7_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i32 %x, 32768
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i32_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: jne .LBB8_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB8_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i32 %x, 128
+ %r = icmp eq i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i32_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: je .LBB9_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: .LBB9_2: # %f
+; CHECK-NEXT: retq
+entry:
+ %a = and i32 %x, 128
+ %r = icmp ne i32 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i32 [ %x, %entry], [ 42, %t]
+ ret i32 %ret
+}
+
+define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
+; CHECK-LABEL: test_clear_mask_i16_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: jne .LBB10_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movw $42, %ax
+; CHECK-NEXT: .LBB10_2: # %f
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %a = and i16 %x, 128
+ %r = icmp eq i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i16_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testb $-128, %al
+; CHECK-NEXT: je .LBB11_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movw $42, %ax
+; CHECK-NEXT: .LBB11_2: # %f
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %a = and i16 %x, 128
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
+
+define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
+; CHECK-LABEL: test_set_mask_i16_i7:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: testb $64, %al
+; CHECK-NEXT: je .LBB12_2
+; CHECK-NEXT: # %bb.1: # %t
+; CHECK-NEXT: movw $42, %ax
+; CHECK-NEXT: .LBB12_2: # %f
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+entry:
+ %a = and i16 %x, 64
+ %r = icmp ne i16 %a, 0
+ br i1 %r, label %t, label %f
+t:
+ br label %f
+f:
+ %ret = phi i16 [ %x, %entry], [ 42, %t]
+ ret i16 %ret
+}
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