[llvm] e2b4425 - [RISCV][Codegen] Account for LMUL in Vector Mask instructions
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 06:50:17 PST 2022
Author: Michael Maitland
Date: 2022-12-06T06:48:42-08:00
New Revision: e2b44258482a56e8c3f7dbd961c2ab05a07ed143
URL: https://github.com/llvm/llvm-project/commit/e2b44258482a56e8c3f7dbd961c2ab05a07ed143
DIFF: https://github.com/llvm/llvm-project/commit/e2b44258482a56e8c3f7dbd961c2ab05a07ed143.diff
LOG: [RISCV][Codegen] Account for LMUL in Vector Mask instructions
It is likley that subtargets act differently for vector fixed-point arithmetic instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.
Differential Revision: https://reviews.llvm.org/D137427
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 57f5fe3f142ac..5f1e02975bd86 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -717,18 +717,19 @@ multiclass VWREDO_FV_V<string opcodestr, bits<6> funct6> {
}
multiclass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
- def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">,
- Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
+ def M : VALUVVNoVm<funct6, OPMVV, opcodestr #"." #vm #"m">,
+ Sched<[WriteVMALUV_UpperBound, ReadVMALUV_UpperBound,
+ ReadVMALUV_UpperBound]>;
}
multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
- Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>;
+ Sched<[WriteVMSFSV_UpperBound, ReadVMSFSV_UpperBound, ReadVMask]>;
}
multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
- Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
+ Sched<[WriteVMIotV_UpperBound, ReadVMIotV_UpperBound, ReadVMask]>;
}
multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
@@ -1518,13 +1519,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
"vcpop.m", "$vd, $vs2$vm">,
- Sched<[WriteVMPopV, ReadVMPopV, ReadVMask]>;
+ Sched<[WriteVMPopV_UpperBound, ReadVMPopV_UpperBound,
+ ReadVMask]>;
// vfirst find-first-set mask bit
def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
"vfirst.m", "$vd, $vs2$vm">,
- Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMask]>;
+ Sched<[WriteVMFFSV_UpperBound, ReadVMFFSV_UpperBound,
+ ReadVMask]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
@@ -1550,7 +1553,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
let vs2 = 0 in
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
(ins VMaskOp:$vm), "vid.v", "$vd$vm">,
- Sched<[WriteVMIdxV, ReadVMask]>;
+ Sched<[WriteVMIdxV_UpperBound, ReadVMask]>;
// Integer Scalar Move Instructions
let vm = 1, RVVConstraint = NoConstraint in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index aae4db875aac0..f5a2c1fe91166 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1795,11 +1795,14 @@ multiclass VPseudoIStore<bit Ordered> {
multiclass VPseudoVPOP_M {
foreach mti = AllMasks in
{
+ defvar mx = mti.LMul.MX;
+ defvar WriteVMPopV_MX = !cast<SchedWrite>("WriteVMPopV_" # mx);
+ defvar ReadVMPopV_MX = !cast<SchedRead>("ReadVMPopV_" # mx);
let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>,
- Sched<[WriteVMPopV, ReadVMPopV, ReadVMPopV]>;
+ Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask,
- Sched<[WriteVMPopV, ReadVMPopV, ReadVMPopV]>;
+ Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>;
}
}
}
@@ -1807,11 +1810,14 @@ multiclass VPseudoVPOP_M {
multiclass VPseudoV1ST_M {
foreach mti = AllMasks in
{
+ defvar mx = mti.LMul.MX;
+ defvar WriteVMFFSV_MX = !cast<SchedWrite>("WriteVMFFSV_" # mx);
+ defvar ReadVMFFSV_MX = !cast<SchedRead>("ReadVMFFSV_" # mx);
let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>,
- Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMFFSV]>;
+ Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask,
- Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMFFSV]>;
+ Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>;
}
}
}
@@ -1820,33 +1826,45 @@ multiclass VPseudoVSFS_M {
defvar constraint = "@earlyclobber $rd";
foreach mti = AllMasks in
{
+ defvar mx = mti.LMul.MX;
+ defvar WriteVMSFSV_MX = !cast<SchedWrite>("WriteVMSFSV_" # mx);
+ defvar ReadVMSFSV_MX = !cast<SchedRead>("ReadVMSFSV_" # mx);
let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>,
- Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>;
+ Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
- Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>;
+ Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>;
}
}
}
multiclass VPseudoVID_V {
foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVMIdxV_MX = !cast<SchedWrite>("WriteVMIdxV_" # mx);
+ defvar ReadVMIdxV_MX = !cast<SchedRead>("ReadVMIdxV_" # mx);
+
let VLMul = m.value in {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
- Sched<[WriteVMIdxV, ReadVMask]>;
+ Sched<[WriteVMIdxV_MX, ReadVMask]>;
def "_V_" # m.MX # "_TU": VPseudoNullaryNoMaskTU<m.vrclass>,
- Sched<[WriteVMIdxV, ReadVMask]>;
+ Sched<[WriteVMIdxV_MX, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
- Sched<[WriteVMIdxV, ReadVMask]>;
+ Sched<[WriteVMIdxV_MX, ReadVMask]>;
}
}
}
multiclass VPseudoNullaryPseudoM <string BaseInst> {
foreach mti = AllMasks in {
+ defvar mx = mti.LMul.MX;
+ defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
+ defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
+
let VLMul = mti.LMul.value in {
- def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">;
+ def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">,
+ Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
}
}
}
@@ -1854,14 +1872,17 @@ multiclass VPseudoNullaryPseudoM <string BaseInst> {
multiclass VPseudoVIOT_M {
defvar constraint = "@earlyclobber $rd";
foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVMIotV_MX = !cast<SchedWrite>("WriteVMIotV_" # mx);
+ defvar ReadVMIotV_MX = !cast<SchedRead>("ReadVMIotV_" # mx);
let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
- Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
+ Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU<m.vrclass, VR, constraint>,
- Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
+ Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, VR, constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
- Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
+ Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
}
}
}
@@ -2002,11 +2023,16 @@ multiclass VPseudoBinaryV_VI_LMUL<Operand ImmType = simm5, LMULInfo m, string Co
}
multiclass VPseudoVALU_MM {
- foreach m = MxList in
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
+ defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
+
let VLMul = m.value in {
- def "_MM_" # m.MX : VPseudoBinaryNoMask<VR, VR, VR, "", /*DummyMask*/0>,
- Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
+ def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "", /*DummyMask*/0>,
+ Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
}
+ }
}
// We use earlyclobber here due to
@@ -5612,10 +5638,8 @@ defm PseudoVMORN: VPseudoVALU_MM;
defm PseudoVMXNOR: VPseudoVALU_MM;
// Pseudo instructions
-defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">,
- Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
-defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">,
- Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>;
+defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">;
+defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
//===----------------------------------------------------------------------===//
// 16.2. Vector mask population count vcpop
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index aab5cf2b8372d..5c24e8ada4c94 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -309,19 +309,19 @@ def WriteVFWRedOV : SchedWrite;
// 15. Vector Mask Instructions
// 15.1. Vector Mask-Register Logical Instructions
-def WriteVMALUV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMALUV">;
// 15.2. Vector Mask Population Count
-def WriteVMPopV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMPopV">;
// 15.3. Vector Find-First-Set Mask Bit
-def WriteVMFFSV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMFFSV">;
// 15.4. Vector Set-Before-First Mask Bit
// 15.5. Vector Set-Including-First Mask Bit
// 15.6. Vector Set-only-First Mask Bit
-def WriteVMSFSV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMSFSV">;
// 15.8. Vector Iota Instruction
-def WriteVMIotV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMIotV">;
// 15.9. Vector Element Index Instruction
-def WriteVMIdxV : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVMIdxV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
@@ -529,17 +529,17 @@ def ReadVFWRedOV0 : SchedRead;
// 15. Vector Mask Instructions
// 15.1. Vector Mask-Register Logical Instructions
-def ReadVMALUV : SchedRead;
+defm "" : LMULSchedReads<"ReadVMALUV">;
// 15.2. Vector Mask Population Count
-def ReadVMPopV : SchedRead;
+defm "" : LMULSchedReads<"ReadVMPopV">;
// 15.3. Vector Find-First-Set Mask Bit
-def ReadVMFFSV : SchedRead;
+defm "" : LMULSchedReads<"ReadVMFFSV">;
// 15.4. Vector Set-Before-First Mask Bit
// 15.5. Vector Set-Including-First Mask Bit
// 15.6. Vector Set-only-First Mask Bit
-def ReadVMSFSV : SchedRead;
+defm "" : LMULSchedReads<"ReadVMSFSV">;
// 15.8. Vector Iota Instruction
-def ReadVMIotV : SchedRead;
+defm "" : LMULSchedReads<"ReadVMIotV">;
// 16. Vector Permutation Instructions
// 16.1. Integer Scalar Move Instructions
@@ -730,12 +730,12 @@ def : WriteRes<WriteVFWRedV, []>;
def : WriteRes<WriteVFWRedOV, []>;
// 15. Vector Mask Instructions
-def : WriteRes<WriteVMALUV, []>;
-def : WriteRes<WriteVMPopV, []>;
-def : WriteRes<WriteVMFFSV, []>;
-def : WriteRes<WriteVMSFSV, []>;
-def : WriteRes<WriteVMIotV, []>;
-def : WriteRes<WriteVMIdxV, []>;
+defm "" : LMULWriteRes<"WriteVMALUV", []>;
+defm "" : LMULWriteRes<"WriteVMPopV", []>;
+defm "" : LMULWriteRes<"WriteVMFFSV", []>;
+defm "" : LMULWriteRes<"WriteVMSFSV", []>;
+defm "" : LMULWriteRes<"WriteVMIotV", []>;
+defm "" : LMULWriteRes<"WriteVMIdxV", []>;
// 16. Vector Permutation Instructions
def : WriteRes<WriteVIMovVX, []>;
@@ -885,11 +885,11 @@ def : ReadAdvance<ReadVFWRedOV, 0>;
def : ReadAdvance<ReadVFWRedOV0, 0>;
// 15. Vector Mask Instructions
-def : ReadAdvance<ReadVMALUV, 0>;
-def : ReadAdvance<ReadVMPopV, 0>;
-def : ReadAdvance<ReadVMFFSV, 0>;
-def : ReadAdvance<ReadVMSFSV, 0>;
-def : ReadAdvance<ReadVMIotV, 0>;
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
// 16. Vector Permutation Instructions
def : ReadAdvance<ReadVIMovVX, 0>;
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