[PATCH] D138521: [X86] Support ANDNP combine through broadcast instructions with scalar input

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48169
+                                    const X86Subtarget &Subtarget) {
+  assert(N->getOpcode() == ISD::AND);
+
----------------
(style) Missing assert message


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48173
+  if (!((VT.is128BitVector() && Subtarget.hasSSE2()) ||
+        (VT.is256BitVector() && Subtarget.hasInt256()) ||
+        (VT.is512BitVector() && Subtarget.useAVX512Regs())))
----------------
256-bit vectors should be OK on AVX1 - but OK to just add a TODO if there's no current test coverage.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48180
+    if (SVN && SVN->hasOneUse() && SVN->isSplat() &&
+        SVN->getOperand(1).isUndef()) {
+      SDValue IVEN = SVN->getOperand(0);
----------------
(style) Use early-out instead of nested ifs (and move oneuse to the end as its the most expensive call)
```
if (!SVN || !SVN->isSplat() || !SVN->getOperand(1).isUndef() || !SVN->hasOneUse())
  return SDValue();
```


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:48205
+static SDValue combineAndNot(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::AND);
+
----------------
(style) Missing assert message


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138521/new/

https://reviews.llvm.org/D138521