[PATCH] D138904: [AArch64] Transform shift+and to shift+shift to select more shifted register

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

>From what I can tell I think the code is OK. LGTM

This doesn't come up often, but I do see it triggering. I'm not sure what the motivating case is but it seemed OK for performance in the tests I ran.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:633-634
+  uint64_t ShiftAmtC = ShiftAmtNode->getZExtValue();
+  SDValue RHS = N.getOperand(1);
+  ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
+  if (!RHSC)
----------------
If RHS isnt used anywhere else:
ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N.getOperand(1));


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:658
+    NewShiftC = LowZBits + ShiftAmtC;
+    if (NewShiftC >= BitWidth)
+      return false;
----------------
Some more comments explaining these conditions would be good.


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https://reviews.llvm.org/D138904