[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+                     [FeatureRV32E, FeatureStdExtC],
+                     [TuneNoDefaultUnroll]>;
----------------
dnpetrov-sc wrote:
> craig.topper wrote:
> > Shouldn't this also need Feature32Bit?
> Now, that's somewhat funny. Indeed, RISCVSubtarget has `HasRV32` field, but it is never queried. `IsRV32` predicate in RISCV.td is mapped to `!Subtarget->is64Bit()` in C++ code.
> 
> Code generation for RV32E is not implemented yet, though (and would error out in `RISCVTargetLowering`). I'll drop scr1-min for now.
> 
It is queried from the MC layer using something like FeatureBits[RISCV::Feature32Bit].

It’s only there to distinquish mtune CPU names from real CPU names. The mtune CPU names don’t have 32Bit or 64Bit and generate an error if they are used with -mcpu


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  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302