[PATCH] D139398: [AMDGPU] Add bf16 storage support

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh created this revision.
Pierre-vh added reviewers: arsenm, foad, yaxunl.
Herald added subscribers: kosarev, kerbowa, hiraditya, tpr, dstuttard, jvesely, kzhuravl.
Herald added a project: All.
Pierre-vh requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wdng.
Herald added projects: clang, LLVM.

- [Clang] Declare AMDGPU target as supporting BF16 for storage-only purposes.
  - Add Sema & CodeGen tests cases.
  - Also add cases that D138651 <https://reviews.llvm.org/D138651> would have covered as this patch replaces it.
- [AMDGPU] Add BF16 storage-only support
  - CC: Add bf16/v2bf16 arguments support by converting them to i16/i32.
  - Add BF16 to various register classes & fix issues it causes with type inference.
  - DAG: Add BF16 legalization/codegen support for GCN targets.
  - GISel: Not supported as the framework doesn't support bfloat16 properly yet.
  - Added test cases for supported BF16 ops + unsupported ones.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139398

Files:
  clang/lib/Basic/Targets/AMDGPU.cpp
  clang/lib/Basic/Targets/AMDGPU.h
  clang/test/CodeGenCUDA/amdgpu-bf16.cu
  clang/test/SemaCUDA/amdgpu-bf16.cu
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/VOP3PInstructions.td
  llvm/test/CodeGen/AMDGPU/bf16-ops.ll
  llvm/test/CodeGen/AMDGPU/bf16.ll

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