[llvm] f7a46aa - [RISCV] Fold vector binary operatrion into select with identity constant.
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 5 19:19:39 PST 2022
Author: jacquesguan
Date: 2022-12-06T11:19:31+08:00
New Revision: f7a46aa8fbc261f2c399f192902bfccce57f35e7
URL: https://github.com/llvm/llvm-project/commit/f7a46aa8fbc261f2c399f192902bfccce57f35e7
DIFF: https://github.com/llvm/llvm-project/commit/f7a46aa8fbc261f2c399f192902bfccce57f35e7.diff
LOG: [RISCV] Fold vector binary operatrion into select with identity constant.
This patch implements shouldFoldSelectWithIdentityConstant for RISCV. It would try to generate vmerge after the binary instruction and let them folded to maksed instruction later.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D131551
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7c8e9f5ce0b4..3db432cd8571 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1228,6 +1228,18 @@ bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
return C && C->getAPIntValue().ule(10);
}
+bool RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(unsigned Opcode,
+ EVT VT) const {
+ // Only enable for rvv.
+ if (!VT.isVector() || !Subtarget.hasVInstructions())
+ return false;
+
+ if (VT.isFixedLengthVector() && !isTypeLegal(VT))
+ return false;
+
+ return true;
+}
+
bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const {
assert(Ty->isIntegerTy());
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index a1c79d9ebc06..869bd0f0518e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -393,6 +393,9 @@ class RISCVTargetLowering : public TargetLowering {
CallingConv::ID CC,
EVT VT) const override;
+ bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
+ EVT VT) const override;
+
/// Return true if the given shuffle mask can be codegen'd directly, or if it
/// should be stack expanded.
bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
index 4e7d778ff645..cb30e1fcae9b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
@@ -894,10 +894,8 @@ define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = add <vscale x 8 x i32> %va, %vs
@@ -907,10 +905,8 @@ define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -922,10 +918,8 @@ define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vadd_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vadd.vi v8, v8, 7, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
index e8566954a347..2ac0b32feaf9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
@@ -1385,10 +1385,8 @@ define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, -1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1400,10 +1398,8 @@ define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, -1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1417,10 +1413,8 @@ define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vand_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, -1
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 7, v0.t
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
%allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
index 7f0be9299cac..bf9edd47fda3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
@@ -373,10 +373,8 @@ define <vscale x 8 x double> @vfadd_fv_nxv8f64(<vscale x 8 x double> %va, double
define <vscale x 8 x float> @vfadd_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfadd_vv_mask_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vfadd.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfadd.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
@@ -388,10 +386,8 @@ define <vscale x 8 x float> @vfadd_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vs
define <vscale x 8 x float> @vfadd_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfadd_vf_mask_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
-; CHECK-NEXT: vfadd.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfadd.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
index 544a3c1e6982..bf7cbedb6f6c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
@@ -373,10 +373,8 @@ define <vscale x 8 x double> @vfsub_fv_nxv8f64(<vscale x 8 x double> %va, double
define <vscale x 8 x float> @vfsub_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfsub_vv_mask_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vfsub.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
@@ -388,10 +386,8 @@ define <vscale x 8 x float> @vfsub_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vs
define <vscale x 8 x float> @vfsub_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vfsub_vf_mask_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
-; CHECK-NEXT: vfsub.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfsub.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
%splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
index ec6d314dfe98..0394cf4f977c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
@@ -963,10 +963,8 @@ define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmul.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -978,10 +976,8 @@ define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -995,10 +991,9 @@ define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vmul_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: li a0, 7
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
%one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
index 69f72614cae4..bf6a8b96b225 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
@@ -1178,10 +1178,8 @@ define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = or <vscale x 8 x i32> %va, %vs
@@ -1191,10 +1189,8 @@ define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x
define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1206,10 +1202,8 @@ define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signe
define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vor_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vor.vi v8, v8, 7, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
index 6869eff6a2c7..93f43f4578dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
@@ -633,10 +633,8 @@ define <vscale x 8 x i64> @vshl_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vv_mask_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = shl <vscale x 8 x i32> %va, %vs
@@ -646,10 +644,8 @@ define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -661,11 +657,8 @@ define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vshl_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 31, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
index 73406a98b1a9..743031616967 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
@@ -805,10 +805,8 @@ define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vv_mask_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = ashr <vscale x 8 x i32> %va, %vs
@@ -818,10 +816,8 @@ define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -833,11 +829,8 @@ define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsra_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsra.vi v8, v8, 31, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
index 8cb5584ac694..be70b20181b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
@@ -585,10 +585,8 @@ define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i32> %va, %vs
@@ -598,10 +596,8 @@ define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -613,11 +609,8 @@ define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 31, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
index 5d6c3f4741b6..6a7b2a4658e2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
@@ -872,10 +872,8 @@ define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
@@ -886,10 +884,8 @@ define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -901,10 +897,9 @@ define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vsub_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: li a0, 7
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
index 0518a5a87b1d..8171ddae953c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
@@ -1385,10 +1385,8 @@ define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vv_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vxor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
%vc = xor <vscale x 8 x i32> %va, %vs
@@ -1398,10 +1396,8 @@ define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vx_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vxor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1413,10 +1409,8 @@ define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 sign
define <vscale x 8 x i32> @vxor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
; CHECK-LABEL: vxor_vi_mask_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
-; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
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