[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:314
+    case ISD::SRA:
+      Opc = AVRISD::ASRW;
+      break;
----------------
aykevl wrote:
> benshi001 wrote:
> > Would it better to use `std::map` or equivalent but more efficient llvm utilities?
> Do you know of any?
> Other code seems to use a `switch` and I think this is very readable.
Though `switch` is more readable, it seems boring, in my opinion. 

So I suggest

```
  std::map<unsigned, unsigned> OpMap = {{ISD::SHL, AVRISD::LSLW},
                                        {ISD::SRL, AVRISD::LSRW}, 
                                        {ISD::SRA, AVRISD::ASRW}};
  assert(OpMap.find(Op.getOpcode()) != OpMap.end() &&
         "Unexpected shift opcode");
  unsigned Opc = OpMap[Op.getOpcode()];
```

which looks more clear.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529