[llvm] 6392cf3 - [RISCV][test] Add pre-commit test for D131551.
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 5 18:38:33 PST 2022
Author: jacquesguan
Date: 2022-12-06T10:38:25+08:00
New Revision: 6392cf331a9b7ab85f0c37b3a1468bc7f1d14a0b
URL: https://github.com/llvm/llvm-project/commit/6392cf331a9b7ab85f0c37b3a1468bc7f1d14a0b
DIFF: https://github.com/llvm/llvm-project/commit/6392cf331a9b7ab85f0c37b3a1468bc7f1d14a0b.diff
LOG: [RISCV][test] Add pre-commit test for D131551.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D131950
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
index 890972bf4f6da..4e7d778ff6452 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
@@ -890,3 +890,76 @@ define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = add <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = add <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = add <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = add <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vv_mask_negative0_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vv_mask_negative0_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+ %vc = add <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vv_mask_negative1_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vv_mask_negative1_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = add <vscale x 8 x i32> %va, %vs
+ %vd = add <vscale x 8 x i32> %vc, %vs
+ ret <vscale x 8 x i32> %vd
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
index edd644a5275fa..e8566954a3475 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
@@ -1381,3 +1381,52 @@ define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = and <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, -1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %allones = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %allones
+ %vc = and <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, -1
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+ %vc = and <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, -1
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vand.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+ %vc = and <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
index 61954b826ede2..5e32e551ba0dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
@@ -1184,3 +1184,52 @@ define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
%vc = sdiv <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+define <vscale x 8 x i32> @vdiv_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+ %vc = sdiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = sdiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = sdiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
index 6f8a5ac39414c..df80e60cfca18 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
@@ -1197,3 +1197,52 @@ define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x
%vd = udiv <vscale x 8 x i64> %va, %vc
ret <vscale x 8 x i64> %vd
}
+
+define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+ %vc = udiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = udiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = udiv <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
index d9c73dfd31a23..7f0be9299cacb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
@@ -369,3 +369,35 @@ define <vscale x 8 x double> @vfadd_fv_nxv8f64(<vscale x 8 x double> %va, double
%vc = fadd <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}
+
+define <vscale x 8 x float> @vfadd_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfadd_vv_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vfadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
+ %vc = fadd fast <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
+
+define <vscale x 8 x float> @vfadd_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfadd_vf_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
+; CHECK-NEXT: vfadd.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
+ %splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
+ %vc = fadd fast <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
index c99ed6267927d..24dd8291247b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
@@ -369,3 +369,35 @@ define <vscale x 8 x double> @vfdiv_fv_nxv8f64(<vscale x 8 x double> %va, double
%vc = fdiv <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}
+
+define <vscale x 8 x float> @vfdiv_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfdiv_vv_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vfdiv.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
+ %vc = fdiv <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
+
+define <vscale x 8 x float> @vfdiv_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfdiv_vf_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
+; CHECK-NEXT: vfdiv.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
+ %splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
+ %vc = fdiv <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
index 7aec35194466f..24f87ede34d79 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
@@ -369,3 +369,35 @@ define <vscale x 8 x double> @vfmul_fv_nxv8f64(<vscale x 8 x double> %va, double
%vc = fmul <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}
+
+define <vscale x 8 x float> @vfmul_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfmul_vv_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vfmul.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
+ %vc = fmul <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
+
+define <vscale x 8 x float> @vfmul_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfmul_vf_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
+; CHECK-NEXT: vfmul.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
+ %splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
+ %vc = fmul <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
index f4bba98b293da..544a3c1e6982b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
@@ -369,3 +369,35 @@ define <vscale x 8 x double> @vfsub_fv_nxv8f64(<vscale x 8 x double> %va, double
%vc = fsub <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}
+
+define <vscale x 8 x float> @vfsub_vv_mask_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfsub_vv_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vfsub.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %vb, <vscale x 8 x float> %splat
+ %vc = fsub fast <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
+
+define <vscale x 8 x float> @vfsub_vf_mask_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vfsub_vf_mask_nxv8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0
+; CHECK-NEXT: vfsub.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x float> poison, float 0.0, i32 0
+ %splat0 = shufflevector <vscale x 8 x float> %head0, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x float> poison, float %b, i32 0
+ %splat1 = shufflevector <vscale x 8 x float> %head1, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x float> %splat1, <vscale x 8 x float> %splat0
+ %vc = fsub fast <vscale x 8 x float> %va, %vs
+ ret <vscale x 8 x float> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
index 61ab1b1a962c8..a6693fad8dd5f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
@@ -890,3 +890,48 @@ define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i32> @vmax_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vmaxu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vmaxu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, -3, v0
+; CHECK-NEXT: vmaxu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
index e8c16997efe0d..2fbe87742a4c4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
@@ -890,3 +890,54 @@ define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i32> @vmin_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, -1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vminu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %max = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %max
+ %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, -1
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vminu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+ %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, -1
+; CHECK-NEXT: vmerge.vim v12, v12, -3, v0
+; CHECK-NEXT: vminu.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+ %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+ %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+ %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
index f3e79cfb7933f..ec6d314dfe987 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
@@ -959,3 +959,53 @@ define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = mul <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 1
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+ %vc = mul <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = mul <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 1
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vmul.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+ %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+ %vc = mul <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
index 663caedd115f8..69f72614cae48 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
@@ -1174,3 +1174,46 @@ define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = or <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = or <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = or <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = or <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
index 53c876bf98a7c..6869eff6a2c7f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
@@ -629,3 +629,47 @@ define <vscale x 8 x i64> @vshl_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
%vc = shl <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vv_mask_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsll.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
index fb20fc72bdc94..73406a98b1a94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
@@ -802,3 +802,46 @@ define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vv_mask_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsra.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = ashr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
index 32e75adbe5ab2..8cb5584ac6941 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
@@ -582,3 +582,46 @@ define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = lshr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = lshr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsrl.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = lshr <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
index 0fac30943d1dd..5d6c3f4741b63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
@@ -868,3 +868,47 @@ define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = sub <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: ret
+
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vsub.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = sub <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
index 2e64cdf39c4f8..0518a5a87b1d9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
@@ -1381,3 +1381,46 @@ define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
%v = xor <vscale x 8 x i64> %splat1, %splat2
ret <vscale x 8 x i64> %v
}
+
+define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vv_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vx_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
+; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vi_mask_nxv8i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 7, v0
+; CHECK-NEXT: vxor.vv v8, v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+ %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+ %vc = xor <vscale x 8 x i32> %va, %vs
+ ret <vscale x 8 x i32> %vc
+}
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