[PATCH] D139363: [SDAG] try to convert bit set/clear to signbit test when trunc is free

[Sanjay Patel via Phabricator via llvm-commits]

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This was noted as a regression in the post-commit feedback for D112634 <https://reviews.llvm.org/D112634> (where we canonicalized IR differently).

For x86, this saves a few instruction bytes. AArch64 seems neutral. There's an improvement on RISCV (but it doesn't show up in the tests added specifically to test this patch - possibly because the pattern is converted to use a shift before we try to match it or the TLI hooks are not triggering).

There is a slight regression on an x86 test in "is_fpclass" - that suggests we could try harder to convert to a right-shift, but maybe only if the setcc result is used in some subsequent math/logic.


https://reviews.llvm.org/D139363

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/signbit-test.ll
  llvm/test/CodeGen/RISCV/bittest.ll
  llvm/test/CodeGen/X86/btq.ll
  llvm/test/CodeGen/X86/is_fpclass-fp80.ll
  llvm/test/CodeGen/X86/masked_compressstore.ll
  llvm/test/CodeGen/X86/masked_expandload.ll
  llvm/test/CodeGen/X86/masked_gather.ll
  llvm/test/CodeGen/X86/masked_load.ll
  llvm/test/CodeGen/X86/masked_store.ll
  llvm/test/CodeGen/X86/masked_store_trunc.ll
  llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
  llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
  llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
  llvm/test/CodeGen/X86/signbit-test.ll
  llvm/test/CodeGen/X86/test-vs-bittest.ll

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