[PATCH] D137140: [SDAG] Allow scalable vectors in ComputeKnownBits

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Ok, I think this is a Hexagon target bug.  What's going on here is that Hexagon appears to be using SPLAT_VECTOR for fixed length vector types, and are legalizing build_vector splats of narrow types to SPLAT_VECTOR of i32.

The problem is that this doesn't work.  Generic DAG combine canonicalizes the other way given known bits information.  Before this change, that wasn't *visible* and didn't kick in because generic DAG couldn't see the SPLAT_VALUE known bits, but that's it.

I'm going to remove the implicit truncation support in SPLAT_VECTOR from this patch (that hides the above bug), and then check this in again.  Someone on the Hexagon side should definite figure out how to fix this properly and add back the implicit truncation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137140/new/

https://reviews.llvm.org/D137140