[PATCH] D138812: [AArch64] lower abs intrinsic to new ABS instruction in SelDag

[Ties Stuij via Phabricator via llvm-commits]

stuij marked 4 inline comments as done.
stuij added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:7269
+                          SDPatternOperator OpNode = null_frag,
+                          Predicate pred = IsTrue> {
   def v1i64       : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
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lenary wrote:
> This would be equivalent and neater, and allow multiple predicates.
That syntax isn't quite right, as Predicates isn't a list, but I appreciate the idea. Changed the code in the spririt of your idea.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:7274
+  let Predicates = [pred] in {
   def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
             (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
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dmgreen wrote:
> I'm not sure this pattern will be used for anything. It can probably just be removed without modifying any tests.
Thanks! I prefer to create another patch for that as I feel it just falls outside of the scope of this patch.


Repository:
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  https://reviews.llvm.org/D138812/new/

https://reviews.llvm.org/D138812