[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:291
+      // 32-bit shifts are converted to a loop in IR.
+      llvm_unreachable("Expected a constant shift!");
+    }
----------------
```
llvm_unreachable("Expected a constant shift amount!");
```


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:302
+        cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8);
+    unsigned Opc;
----------------
It is OK that  `ShiftAmount` have a `MVT::i8` type ? Could it be better to `MVT::i16` ?


================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:314
+    case ISD::SRA:
+      Opc = AVRISD::ASRW;
+      break;
----------------
Would it better to use `std::map` or equivalent but more efficient llvm utilities?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529