[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1963
+    Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
+    BuildMI(*BB, MI, dl, TII.get(AVR::COPY), Out).addReg(AVR::R1);
+    Regs[Regs.size() - 1] = std::pair(Out, 0);
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How about using `GetZeroRegister()` instead of fixed `AVR::R1`? This way should also fit avrtiny. Or we can  emit `eor Rx, Rx` instead of `mov Rx, Zero` .


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  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529