[PATCH] D139301: [X86] Add scheduling info of CodeGenOnly but encodable instructions for AlderlakeP model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added inline comments.


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Comment at: llvm/lib/Target/X86/X86SchedAlderlakeP.td:812-814
+def : InstRW<[ADLPWriteResGroup38, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
+def : InstRW<[ADLPWriteResGroup38, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup38, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
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CVTSI642SSrr has different schedreadwrite with CVTSI642SSrr_Int?
I think they should be same.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139301/new/

https://reviews.llvm.org/D139301