[PATCH] D138529: [AVR] Optimize constant 32-bit shifts

[Ben Shi via Phabricator via llvm-commits]

benshi001 added inline comments.


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Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:286
   assert(isPowerOf2_32(VT.getSizeInBits()) &&
          "Expected power-of-2 shift amount");
 
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This message should be `Expected power-of-2 shift operand`, you can also fix it along with your patch..


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Comment at: llvm/lib/Target/AVR/AVRISelLowering.h:42
   LSLHI,   ///< Higher 8-bit of word logical shift left.
+  LSLW,    ///< Wide logical shift left.
   LSR,     ///< Logical shift right.
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`LSLW` is a bit confusing with `LSLWN`, so how about `LSLWP`, which means `LSLW-Pair`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138529/new/

https://reviews.llvm.org/D138529