[PATCH] D138529: [AVR] Optimize constant 32-bit shifts
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 4 23:40:54 PST 2022
benshi001 added inline comments.
================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:286
assert(isPowerOf2_32(VT.getSizeInBits()) &&
"Expected power-of-2 shift amount");
----------------
This message should be `Expected power-of-2 shift operand`, you can also fix it along with your patch..
================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.h:42
LSLHI, ///< Higher 8-bit of word logical shift left.
+ LSLW, ///< Wide logical shift left.
LSR, ///< Logical shift right.
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`LSLW` is a bit confusing with `LSLWN`, so how about `LSLWP`, which means `LSLW-Pair`.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138529/new/
https://reviews.llvm.org/D138529
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