[llvm] 20cde15 - [Target] Use std::nullopt instead of None (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 2 20:36:20 PST 2022
Author: Kazu Hirata
Date: 2022-12-02T20:36:06-08:00
New Revision: 20cde15415d2b2d1b489b4cd5c520c6a8d7f8f54
URL: https://github.com/llvm/llvm-project/commit/20cde15415d2b2d1b489b4cd5c520c6a8d7f8f54
DIFF: https://github.com/llvm/llvm-project/commit/20cde15415d2b2d1b489b4cd5c520c6a8d7f8f54.diff
LOG: [Target] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated. The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Added:
Modified:
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMFastISel.cpp
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/Hexagon/HexagonDepArch.h
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/lib/Target/Mips/MipsInstrInfo.cpp
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/lib/Target/Mips/MipsTargetMachine.cpp
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
llvm/lib/Target/VE/VECustomDAG.cpp
llvm/lib/Target/VE/VECustomDAG.h
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/lib/Target/X86/X86FrameLowering.h
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86LowerAMXType.cpp
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/lib/Target/X86/X86PreAMXConfig.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 245a2e6077a47..75a70c3cd2d78 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -256,7 +256,7 @@ void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
void AArch64AsmPrinter::emitFunctionHeaderComment() {
const AArch64FunctionInfo *FI = MF->getInfo<AArch64FunctionInfo>();
Optional<std::string> OutlinerString = FI->getOutliningStyle();
- if (OutlinerString != None)
+ if (OutlinerString != std::nullopt)
OutStreamer->getCommentOS() << ' ' << OutlinerString;
}
diff --git a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
index 2328a8b4deb82..ac8d753ac4e13 100644
--- a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
@@ -78,7 +78,7 @@ AArch64CompressJumpTables::computeBlockSize(MachineBasicBlock &MBB) {
// computing a size and bail out.
if (MI.getOpcode() == AArch64::INLINEASM ||
MI.getOpcode() == AArch64::INLINEASM_BR)
- return None;
+ return std::nullopt;
Size += TII->getInstSizeInBytes(MI);
}
return Size;
diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
index 6de3741254669..418b201437bf3 100644
--- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
@@ -242,7 +242,7 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
- return None;
+ return std::nullopt;
case AArch64::LD1i64:
case AArch64::LD2i64:
@@ -645,7 +645,7 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
// Loads from the stack pointer don't get prefetched.
Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
- return None;
+ return std::nullopt;
LoadInfo LI;
LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();
@@ -665,7 +665,7 @@ static Optional<unsigned> getTag(const TargetRegisterInfo *TRI,
Off = 0;
else if (LI.OffsetOpnd->isGlobal() || LI.OffsetOpnd->isSymbol() ||
LI.OffsetOpnd->isCPI())
- return None;
+ return std::nullopt;
else if (LI.OffsetOpnd->isReg())
Off = (1 << 5) | TRI->getEncodingValue(LI.OffsetOpnd->getReg());
else
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 3a85cfe5047d3..4d2faaa97d89f 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3576,7 +3576,7 @@ void TagStoreEdit::emitCode(MachineBasicBlock::iterator &InsertI,
*MF, FirstTagStore.Offset, false /*isFixed*/, false /*isSVE*/, Reg,
/*PreferFP=*/false, /*ForSimm=*/true);
FrameReg = Reg;
- FrameRegUpdate = None;
+ FrameRegUpdate = std::nullopt;
mergeMemRefs(TagStores, CombinedMemRefs);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 184ea8e336d84..89a7d72a5cac9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4336,12 +4336,12 @@ static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
static Optional<uint64_t> getConstantLaneNumOfExtractHalfOperand(SDValue &Op) {
SDNode *OpNode = Op.getNode();
if (OpNode->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
- return None;
+ return std::nullopt;
EVT VT = OpNode->getOperand(0).getValueType();
ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpNode->getOperand(1));
if (!VT.isFixedLengthVector() || VT.getVectorNumElements() != 2 || !C)
- return None;
+ return std::nullopt;
return C->getZExtValue();
}
@@ -4664,7 +4664,7 @@ static Optional<SMEAttrs> getCalleeAttrsFromExternalFunction(SDValue V) {
if (S == "__arm_tpidr2_restore")
return SMEAttrs(SMEAttrs::SM_Compatible | SMEAttrs::ZA_Shared);
}
- return None;
+ return std::nullopt;
}
SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
@@ -4824,7 +4824,7 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getConstantOperandVal(2) - Op.getConstantOperandVal(1);
Optional<unsigned> PredPattern =
getSVEPredPatternFromNumElements(NumActiveElems);
- if ((PredPattern != None) &&
+ if ((PredPattern != std::nullopt) &&
NumActiveElems <= (MinSVEVectorSize / ElementSize))
return getPTrue(DAG, dl, Op.getValueType(), *PredPattern);
}
@@ -9014,7 +9014,7 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
Optional<unsigned> PredPattern;
if (Ty.isScalableVector() && IdxVal < 0 &&
(PredPattern = getSVEPredPatternFromNumElements(std::abs(IdxVal))) !=
- None) {
+ std::nullopt) {
SDLoc DL(Op);
// Create a predicate where all but the last -IdxVal elements are false.
@@ -16964,10 +16964,10 @@ static bool isCMP(SDValue Op) {
// (CSEL 0 1 CC Cond) => !CC
static std::optional<AArch64CC::CondCode> getCSETCondCode(SDValue Op) {
if (Op.getOpcode() != AArch64ISD::CSEL)
- return None;
+ return std::nullopt;
auto CC = static_cast<AArch64CC::CondCode>(Op.getConstantOperandVal(2));
if (CC == AArch64CC::AL || CC == AArch64CC::NV)
- return None;
+ return std::nullopt;
SDValue OpLHS = Op.getOperand(0);
SDValue OpRHS = Op.getOperand(1);
if (isOneConstant(OpLHS) && isNullConstant(OpRHS))
@@ -16975,7 +16975,7 @@ static std::optional<AArch64CC::CondCode> getCSETCondCode(SDValue Op) {
if (isNullConstant(OpLHS) && isOneConstant(OpRHS))
return getInvertedCondCode(CC);
- return None;
+ return std::nullopt;
}
// (ADC{S} l r (CMP (CSET HS carry) 1)) => (ADC{S} l r carry)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 745c4237fdd21..9752019b47aa5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1652,10 +1652,10 @@ llvm::examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
SmallVectorImpl<MachineInstr *> *CCUseInstrs) {
MachineBasicBlock *CmpParent = CmpInstr.getParent();
if (MI.getParent() != CmpParent)
- return None;
+ return std::nullopt;
if (areCFlagsAliveInSuccessors(CmpParent))
- return None;
+ return std::nullopt;
UsedNZCV NZCVUsedAfterCmp;
for (MachineInstr &Instr : instructionsWithoutDebug(
@@ -1663,7 +1663,7 @@ llvm::examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
if (Instr.readsRegister(AArch64::NZCV, &TRI)) {
AArch64CC::CondCode CC = findCondCodeUsedByInstr(Instr);
if (CC == AArch64CC::Invalid) // Unsupported conditional instruction
- return None;
+ return std::nullopt;
NZCVUsedAfterCmp |= getUsedNZCV(CC);
if (CCUseInstrs)
CCUseInstrs->push_back(&Instr);
@@ -2601,10 +2601,10 @@ AArch64InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
int64_t Offset; // Filled with the offset of MI.
bool OffsetIsScalable;
if (!getMemOperandWithOffset(MemI, Base, Offset, OffsetIsScalable, TRI))
- return None;
+ return std::nullopt;
if (!Base->isReg())
- return None;
+ return std::nullopt;
ExtAddrMode AM;
AM.BaseReg = Base->getReg();
AM.Displacement = Offset;
@@ -8097,7 +8097,7 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
}
- return None;
+ return std::nullopt;
}
Optional<RegImmPair> AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
@@ -8109,11 +8109,11 @@ Optional<RegImmPair> AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
// destination register.
const MachineOperand &Op0 = MI.getOperand(0);
if (!Op0.isReg() || Reg != Op0.getReg())
- return None;
+ return std::nullopt;
switch (MI.getOpcode()) {
default:
- return None;
+ return std::nullopt;
case AArch64::SUBWri:
case AArch64::SUBXri:
case AArch64::SUBSWri:
@@ -8127,7 +8127,7 @@ Optional<RegImmPair> AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
// TODO: Third operand can be global address (usually some string).
if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
!MI.getOperand(2).isImm())
- return None;
+ return std::nullopt;
int Shift = MI.getOperand(3).getImm();
assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
Offset = Sign * (MI.getOperand(2).getImm() << Shift);
@@ -8145,7 +8145,7 @@ describeORRLoadedValue(const MachineInstr &MI, Register DescribedReg,
const TargetRegisterInfo *TRI) {
auto DestSrc = TII->isCopyInstr(MI);
if (!DestSrc)
- return None;
+ return std::nullopt;
Register DestReg = DestSrc->Destination->getReg();
Register SrcReg = DestSrc->Source->getReg();
@@ -8171,7 +8171,7 @@ describeORRLoadedValue(const MachineInstr &MI, Register DescribedReg,
assert(!TRI->isSuperOrSubRegisterEq(DestReg, DescribedReg) &&
"Unhandled ORR[XW]rs copy case");
- return None;
+ return std::nullopt;
}
Optional<ParamLoadedValue>
@@ -8185,10 +8185,10 @@ AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI,
// MOVZWi may be used for producing zero-extended 32-bit immediates in
// 64-bit parameters, so we need to consider super-registers.
if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
- return None;
+ return std::nullopt;
if (!MI.getOperand(1).isImm())
- return None;
+ return std::nullopt;
int64_t Immediate = MI.getOperand(1).getImm();
int Shift = MI.getOperand(2).getImm();
return ParamLoadedValue(MachineOperand::CreateImm(Immediate << Shift),
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 3b0024e2d39c3..2aaab7652721a 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -99,7 +99,7 @@ using LdStPairFlags = struct LdStPairFlags {
// If not none, RenameReg can be used to rename the result register of the
// first store in a pair. Currently this only works when merging stores
// forward.
- Optional<MCPhysReg> RenameReg = None;
+ Optional<MCPhysReg> RenameReg = std::nullopt;
LdStPairFlags() = default;
@@ -110,7 +110,7 @@ using LdStPairFlags = struct LdStPairFlags {
int getSExtIdx() const { return SExtIdx; }
void setRenameReg(MCPhysReg R) { RenameReg = R; }
- void clearRenameReg() { RenameReg = None; }
+ void clearRenameReg() { RenameReg = std::nullopt; }
Optional<MCPhysReg> getRenameReg() const { return RenameReg; }
};
@@ -1509,7 +1509,7 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
}
LLVM_DEBUG(dbgs() << "No rename register found from "
<< TRI->getRegClassName(RegClass) << "\n");
- return None;
+ return std::nullopt;
}
/// Scan the instructions looking for a load/store that can be combined with the
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 5ee08f5dfdb5a..d377b73234741 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -176,7 +176,7 @@ bool AArch64MIPeepholeOpt::visitAND(
[Opc](T Imm, unsigned RegSize, T &Imm0, T &Imm1) -> Optional<OpcodePair> {
if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1))
return std::make_pair(Opc, Opc);
- return None;
+ return std::nullopt;
},
[&TII = TII](MachineInstr &MI, OpcodePair Opcode, unsigned Imm0,
unsigned Imm1, Register SrcReg, Register NewTmpReg,
@@ -342,7 +342,7 @@ bool AArch64MIPeepholeOpt::visitADDSUB(
return std::make_pair(PosOpc, PosOpc);
if (splitAddSubImm(-Imm, RegSize, Imm0, Imm1))
return std::make_pair(NegOpc, NegOpc);
- return None;
+ return std::nullopt;
},
[&TII = TII](MachineInstr &MI, OpcodePair Opcode, unsigned Imm0,
unsigned Imm1, Register SrcReg, Register NewTmpReg,
@@ -375,13 +375,13 @@ bool AArch64MIPeepholeOpt::visitADDSSUBS(
else if (splitAddSubImm(-Imm, RegSize, Imm0, Imm1))
OP = NegOpcs;
else
- return None;
+ return std::nullopt;
// Check conditional uses last since it is expensive for scanning
// proceeding instructions
MachineInstr &SrcMI = *MRI->getUniqueVRegDef(MI.getOperand(1).getReg());
Optional<UsedNZCV> NZCVUsed = examineCFlagsUse(SrcMI, MI, *TRI);
if (!NZCVUsed || NZCVUsed->C || NZCVUsed->V)
- return None;
+ return std::nullopt;
return OP;
},
[&TII = TII](MachineInstr &MI, OpcodePair Opcode, unsigned Imm0,
diff --git a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
index 7e91dc1b63854..1eebbe0d62f22 100644
--- a/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
@@ -255,7 +255,7 @@ Optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
// - Any other instruction may benefit from being pinned to offset 0.
LLVM_DEBUG(dbgs() << "AArch64StackTaggingPreRA::findFirstSlotCandidate\n");
if (!ClFirstSlot)
- return None;
+ return std::nullopt;
DenseMap<SlotWithTag, int> RetagScore;
SlotWithTag MaxScoreST{-1, -1};
@@ -305,7 +305,7 @@ Optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
}
if (MaxScoreST.FI < 0)
- return None;
+ return std::nullopt;
// If FI's tag is already 0, we are done.
if (MaxScoreST.Tag == 0)
diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
index 64f13eab04132..3ee0d5190ea34 100644
--- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
+++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
@@ -88,7 +88,7 @@ bool AArch64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock *BB)
// If a subtarget does not define resources for STPQi, bail here.
if (SCDesc->isValid() && !SCDesc->isVariant()) {
- unsigned ResLenWithSTP = BBTrace.getResourceLength(None, SCDesc);
+ unsigned ResLenWithSTP = BBTrace.getResourceLength(std::nullopt, SCDesc);
if (ResLenWithSTP > ResLength) {
LLVM_DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber()
<< " resources " << ResLength << " -> " << ResLenWithSTP
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index ed52ea493b933..c96e064acc5ee 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -377,7 +377,7 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
/// Return the cost of the scaling factor used in the addressing
/// mode represented by AM for this target, for a load/store
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 08ef71e3428f3..fe1cd530637e3 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2631,7 +2631,7 @@ static Optional<std::pair<int, int>> parseVectorKind(StringRef Suffix,
}
if (Res == std::make_pair(-1, -1))
- return None;
+ return std::nullopt;
return Optional<std::pair<int, int>>(Res);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 0879826202ca0..8fe70c868d9b2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -1246,7 +1246,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (!determineAndHandleAssignments(
UsingReturnedArg ? ReturnedArgHandler : Handler, Assigner, InArgs,
MIRBuilder, Info.CallConv, Info.IsVarArg,
- UsingReturnedArg ? makeArrayRef(OutArgs[0].Regs) : None))
+ UsingReturnedArg ? makeArrayRef(OutArgs[0].Regs) : std::nullopt))
return false;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index 1f671682cb3bb..79869039fea0b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -23,7 +23,7 @@ AArch64GISelUtils::getAArch64VectorSplat(const MachineInstr &MI,
if (auto Splat = getVectorSplat(MI, MRI))
return Splat;
if (MI.getOpcode() != AArch64::G_DUP)
- return None;
+ return std::nullopt;
Register Src = MI.getOperand(1).getReg();
if (auto ValAndVReg =
getAnyConstantVRegValWithLookThrough(MI.getOperand(1).getReg(), MRI))
@@ -36,7 +36,7 @@ AArch64GISelUtils::getAArch64VectorSplatScalar(const MachineInstr &MI,
const MachineRegisterInfo &MRI) {
auto Splat = getAArch64VectorSplat(MI, MRI);
if (!Splat || Splat->isReg())
- return None;
+ return std::nullopt;
return Splat->getCst();
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 4a0c1e2a1380c..89cb642bdd091 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -217,15 +217,15 @@ class AArch64InstructionSelector : public InstructionSelector {
/// Emit a floating point comparison between \p LHS and \p RHS.
/// \p Pred if given is the intended predicate to use.
- MachineInstr *emitFPCompare(Register LHS, Register RHS,
- MachineIRBuilder &MIRBuilder,
- Optional<CmpInst::Predicate> = None) const;
-
- MachineInstr *emitInstr(unsigned Opcode,
- std::initializer_list<llvm::DstOp> DstOps,
- std::initializer_list<llvm::SrcOp> SrcOps,
- MachineIRBuilder &MIRBuilder,
- const ComplexRendererFns &RenderFns = None) const;
+ MachineInstr *
+ emitFPCompare(Register LHS, Register RHS, MachineIRBuilder &MIRBuilder,
+ Optional<CmpInst::Predicate> = std::nullopt) const;
+
+ MachineInstr *
+ emitInstr(unsigned Opcode, std::initializer_list<llvm::DstOp> DstOps,
+ std::initializer_list<llvm::SrcOp> SrcOps,
+ MachineIRBuilder &MIRBuilder,
+ const ComplexRendererFns &RenderFns = std::nullopt) const;
/// Helper function to emit an add or sub instruction.
///
/// \p AddrModeAndSizeToOpcode must contain each of the opcode variants above
@@ -689,10 +689,10 @@ static Optional<uint64_t> getImmedFromMO(const MachineOperand &Root) {
auto ValAndVReg =
getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
if (!ValAndVReg)
- return None;
+ return std::nullopt;
Immed = ValAndVReg->Value.getSExtValue();
} else
- return None;
+ return std::nullopt;
return Immed;
}
@@ -1795,30 +1795,30 @@ static Optional<int64_t> getVectorShiftImm(Register Reg,
static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) {
Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI);
if (!ShiftImm)
- return None;
+ return std::nullopt;
// Check the immediate is in range for a SHL.
int64_t Imm = *ShiftImm;
if (Imm < 0)
- return None;
+ return std::nullopt;
switch (SrcTy.getElementType().getSizeInBits()) {
default:
LLVM_DEBUG(dbgs() << "Unhandled element type for vector shift");
- return None;
+ return std::nullopt;
case 8:
if (Imm > 7)
- return None;
+ return std::nullopt;
break;
case 16:
if (Imm > 15)
- return None;
+ return std::nullopt;
break;
case 32:
if (Imm > 31)
- return None;
+ return std::nullopt;
break;
case 64:
if (Imm > 63)
- return None;
+ return std::nullopt;
break;
}
return Imm;
@@ -4025,8 +4025,8 @@ bool AArch64InstructionSelector::selectMergeValues(
Register Src1Reg = I.getOperand(1).getReg();
Register Src2Reg = I.getOperand(2).getReg();
auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {});
- MachineInstr *InsMI =
- emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
+ MachineInstr *InsMI = emitLaneInsert(std::nullopt, Tmp.getReg(0), Src1Reg,
+ /* LaneIdx */ 0, RB, MIB);
if (!InsMI)
return false;
MachineInstr *Ins2MI = emitLaneInsert(DstReg, InsMI->getOperand(0).getReg(),
@@ -5216,7 +5216,8 @@ bool AArch64InstructionSelector::selectShuffleVector(
if (DstTy.getSizeInBits() != 128) {
assert(DstTy.getSizeInBits() == 64 && "Unexpected shuffle result ty");
// This case can be done with TBL1.
- MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIB);
+ MachineInstr *Concat =
+ emitVectorConcat(std::nullopt, Src1Reg, Src2Reg, MIB);
if (!Concat) {
LLVM_DEBUG(dbgs() << "Could not do vector concat for tbl1");
return false;
@@ -5388,7 +5389,7 @@ bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I,
// Note that if our vector is already 128 bits, we end up emitting an extra
// register.
MachineInstr *InsMI =
- emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB);
+ emitLaneInsert(std::nullopt, SrcReg, EltReg, LaneIdx, EltRB, MIB);
if (VecSize < 128) {
// If we had to widen to perform the insert, then we have to demote back to
@@ -5564,8 +5565,8 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
for (unsigned i = 2, e = DstSize / EltSize + 1; i < e; ++i) {
// Note that if we don't do a subregister copy, we can end up making an
// extra register.
- PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
- MIB);
+ PrevMI = &*emitLaneInsert(std::nullopt, DstVec, I.getOperand(i).getReg(),
+ i - 1, RB, MIB);
DstVec = PrevMI->getOperand(0).getReg();
}
@@ -5956,8 +5957,8 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectShiftA_32(const MachineOperand &Root) const {
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None || *MaybeImmed > 31)
- return None;
+ if (MaybeImmed == std::nullopt || *MaybeImmed > 31)
+ return std::nullopt;
uint64_t Enc = (32 - *MaybeImmed) & 0x1f;
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
}
@@ -5965,8 +5966,8 @@ AArch64InstructionSelector::selectShiftA_32(const MachineOperand &Root) const {
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectShiftB_32(const MachineOperand &Root) const {
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None || *MaybeImmed > 31)
- return None;
+ if (MaybeImmed == std::nullopt || *MaybeImmed > 31)
+ return std::nullopt;
uint64_t Enc = 31 - *MaybeImmed;
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
}
@@ -5974,8 +5975,8 @@ AArch64InstructionSelector::selectShiftB_32(const MachineOperand &Root) const {
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectShiftA_64(const MachineOperand &Root) const {
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None || *MaybeImmed > 63)
- return None;
+ if (MaybeImmed == std::nullopt || *MaybeImmed > 63)
+ return std::nullopt;
uint64_t Enc = (64 - *MaybeImmed) & 0x3f;
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
}
@@ -5983,8 +5984,8 @@ AArch64InstructionSelector::selectShiftA_64(const MachineOperand &Root) const {
InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectShiftB_64(const MachineOperand &Root) const {
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None || *MaybeImmed > 63)
- return None;
+ if (MaybeImmed == std::nullopt || *MaybeImmed > 63)
+ return std::nullopt;
uint64_t Enc = 63 - *MaybeImmed;
return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}};
}
@@ -6004,7 +6005,7 @@ AArch64InstructionSelector::select12BitValueWithLeftShift(
ShiftAmt = 12;
Immed = Immed >> 12;
} else
- return None;
+ return std::nullopt;
unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
return {{
@@ -6024,8 +6025,8 @@ AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
// here because the ComplexPattern opcode list is only used in
// root-level opcode matching.
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None)
- return None;
+ if (MaybeImmed == std::nullopt)
+ return std::nullopt;
return select12BitValueWithLeftShift(*MaybeImmed);
}
@@ -6036,17 +6037,17 @@ AArch64InstructionSelector::selectNegArithImmed(MachineOperand &Root) const {
// We need a register here, because we need to know if we have a 64 or 32
// bit immediate.
if (!Root.isReg())
- return None;
+ return std::nullopt;
auto MaybeImmed = getImmedFromMO(Root);
- if (MaybeImmed == None)
- return None;
+ if (MaybeImmed == std::nullopt)
+ return std::nullopt;
uint64_t Immed = *MaybeImmed;
// This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
// have the opposite effect on the C flag, so this pattern mustn't match under
// those circumstances.
if (Immed == 0)
- return None;
+ return std::nullopt;
// Check if we're dealing with a 32-bit type on the root or a 64-bit type on
// the root.
@@ -6057,7 +6058,7 @@ AArch64InstructionSelector::selectNegArithImmed(MachineOperand &Root) const {
Immed = ~Immed + 1ULL;
if (Immed & 0xFFFFFFFFFF000000ULL)
- return None;
+ return std::nullopt;
Immed &= 0xFFFFFFULL;
return select12BitValueWithLeftShift(Immed);
@@ -6112,21 +6113,21 @@ AArch64InstructionSelector::selectExtendedSHL(
if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL) {
// Try to look through a ZEXT.
if (OffsetOpc != TargetOpcode::G_ZEXT || !WantsExt)
- return None;
+ return std::nullopt;
OffsetInst = MRI.getVRegDef(OffsetInst->getOperand(1).getReg());
OffsetOpc = OffsetInst->getOpcode();
LookedThroughZExt = true;
if (OffsetOpc != TargetOpcode::G_SHL && OffsetOpc != TargetOpcode::G_MUL)
- return None;
+ return std::nullopt;
}
// Make sure that the memory op is a valid size.
int64_t LegalShiftVal = Log2_32(SizeInBytes);
if (LegalShiftVal == 0)
- return None;
+ return std::nullopt;
if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI))
- return None;
+ return std::nullopt;
// Now, try to find the specific G_CONSTANT. Start by assuming that the
// register we will offset is the LHS, and the register containing the
@@ -6138,13 +6139,13 @@ AArch64InstructionSelector::selectExtendedSHL(
// We didn't get a constant on the RHS. If the opcode is a shift, then
// we're done.
if (OffsetOpc == TargetOpcode::G_SHL)
- return None;
+ return std::nullopt;
// If we have a G_MUL, we can use either register. Try looking at the RHS.
std::swap(OffsetReg, ConstantReg);
ValAndVReg = getIConstantVRegValWithLookThrough(ConstantReg, MRI);
if (!ValAndVReg)
- return None;
+ return std::nullopt;
}
// The value must fit into 3 bits, and must be positive. Make sure that is
@@ -6155,19 +6156,19 @@ AArch64InstructionSelector::selectExtendedSHL(
// a power of 2. If we got a multiply, then we need to check this.
if (OffsetOpc == TargetOpcode::G_MUL) {
if (!isPowerOf2_32(ImmVal))
- return None;
+ return std::nullopt;
// Got a power of 2. So, the amount we'll shift is the log base-2 of that.
ImmVal = Log2_32(ImmVal);
}
if ((ImmVal & 0x7) != ImmVal)
- return None;
+ return std::nullopt;
// We are only allowed to shift by LegalShiftVal. This shift value is built
// into the instruction, so we can't just use whatever we want.
if (ImmVal != LegalShiftVal)
- return None;
+ return std::nullopt;
unsigned SignExtend = 0;
if (WantsExt) {
@@ -6177,12 +6178,12 @@ AArch64InstructionSelector::selectExtendedSHL(
MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI);
auto Ext = getExtendTypeForInst(*ExtInst, MRI, true);
if (Ext == AArch64_AM::InvalidShiftExtend)
- return None;
+ return std::nullopt;
SignExtend = isSignExtendShiftType(Ext) ? 1 : 0;
// We only support SXTW for signed extension here.
if (SignExtend && Ext != AArch64_AM::SXTW)
- return None;
+ return std::nullopt;
OffsetReg = ExtInst->getOperand(1).getReg();
}
@@ -6215,7 +6216,7 @@ InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectAddrModeShiftedExtendXReg(
MachineOperand &Root, unsigned SizeInBytes) const {
if (!Root.isReg())
- return None;
+ return std::nullopt;
MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
// We want to find something like this:
@@ -6233,7 +6234,7 @@ AArch64InstructionSelector::selectAddrModeShiftedExtendXReg(
MachineInstr *PtrAdd =
getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI))
- return None;
+ return std::nullopt;
// Now, try to match an opcode which will match our specific offset.
// We want a G_SHL or a G_MUL.
@@ -6260,13 +6261,13 @@ AArch64InstructionSelector::selectAddrModeRegisterOffset(
// We need a GEP.
MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
if (Gep->getOpcode() != TargetOpcode::G_PTR_ADD)
- return None;
+ return std::nullopt;
// If this is used more than once, let's not bother folding.
// TODO: Check if they are memory ops. If they are, then we can still fold
// without having to recompute anything.
if (!MRI.hasOneNonDBGUse(Gep->getOperand(0).getReg()))
- return None;
+ return std::nullopt;
// Base is the GEP's LHS, offset is its RHS.
return {{[=](MachineInstrBuilder &MIB) {
@@ -6290,11 +6291,11 @@ AArch64InstructionSelector::selectAddrModeXRO(MachineOperand &Root,
unsigned SizeInBytes) const {
MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
if (!Root.isReg())
- return None;
+ return std::nullopt;
MachineInstr *PtrAdd =
getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
if (!PtrAdd)
- return None;
+ return std::nullopt;
// Check for an immediates which cannot be encoded in the [base + imm]
// addressing mode, and can't be encoded in an add/sub. If this happens, we'll
@@ -6319,7 +6320,7 @@ AArch64InstructionSelector::selectAddrModeXRO(MachineOperand &Root,
// mode.
if (ImmOff % SizeInBytes == 0 && ImmOff >= 0 &&
ImmOff < (0x1000 << Scale))
- return None;
+ return std::nullopt;
// Helper lambda to decide whether or not it is preferable to emit an add.
auto isPreferredADD = [](int64_t ImmOff) {
@@ -6340,7 +6341,7 @@ AArch64InstructionSelector::selectAddrModeXRO(MachineOperand &Root,
// If the immediate can be encoded in a single add/sub, then bail out.
if (isPreferredADD(ImmOff) || isPreferredADD(-ImmOff))
- return None;
+ return std::nullopt;
}
// Try to fold shifts into the addressing mode.
@@ -6367,7 +6368,7 @@ AArch64InstructionSelector::selectAddrModeWRO(MachineOperand &Root,
MachineInstr *PtrAdd =
getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
if (!PtrAdd || !isWorthFoldingIntoExtendedReg(*PtrAdd, MRI))
- return None;
+ return std::nullopt;
MachineOperand &LHS = PtrAdd->getOperand(1);
MachineOperand &RHS = PtrAdd->getOperand(2);
@@ -6398,13 +6399,13 @@ AArch64InstructionSelector::selectAddrModeWRO(MachineOperand &Root,
// e.g.
// ldr something, [base_reg, ext_reg, sxtw]
if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI))
- return None;
+ return std::nullopt;
// Check if this is an extend. We'll get an extend type if it is.
AArch64_AM::ShiftExtendType Ext =
getExtendTypeForInst(*OffsetInst, MRI, /*IsLoadStore=*/true);
if (Ext == AArch64_AM::InvalidShiftExtend)
- return None;
+ return std::nullopt;
// Need a 32-bit wide register.
MachineIRBuilder MIB(*PtrAdd);
@@ -6433,28 +6434,28 @@ AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
Root.getParent()->getParent()->getParent()->getRegInfo();
if (!Root.isReg())
- return None;
+ return std::nullopt;
if (!isBaseWithConstantOffset(Root, MRI))
- return None;
+ return std::nullopt;
MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
MachineOperand &OffImm = RootDef->getOperand(2);
if (!OffImm.isReg())
- return None;
+ return std::nullopt;
MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg());
if (RHS->getOpcode() != TargetOpcode::G_CONSTANT)
- return None;
+ return std::nullopt;
int64_t RHSC;
MachineOperand &RHSOp1 = RHS->getOperand(1);
if (!RHSOp1.isCImm() || RHSOp1.getCImm()->getBitWidth() > 64)
- return None;
+ return std::nullopt;
RHSC = RHSOp1.getCImm()->getSExtValue();
// If the offset is valid as a scaled immediate, don't match here.
if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Log2_32(Size)))
- return None;
+ return std::nullopt;
if (RHSC >= -256 && RHSC < 256) {
MachineOperand &Base = RootDef->getOperand(1);
return {{
@@ -6462,7 +6463,7 @@ AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
[=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
}};
}
- return None;
+ return std::nullopt;
}
InstructionSelector::ComplexRendererFns
@@ -6470,23 +6471,23 @@ AArch64InstructionSelector::tryFoldAddLowIntoImm(MachineInstr &RootDef,
unsigned Size,
MachineRegisterInfo &MRI) const {
if (RootDef.getOpcode() != AArch64::G_ADD_LOW)
- return None;
+ return std::nullopt;
MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg());
if (Adrp.getOpcode() != AArch64::ADRP)
- return None;
+ return std::nullopt;
// TODO: add heuristics like isWorthFoldingADDlow() from SelectionDAG.
auto Offset = Adrp.getOperand(1).getOffset();
if (Offset % Size != 0)
- return None;
+ return std::nullopt;
auto GV = Adrp.getOperand(1).getGlobal();
if (GV->isThreadLocal())
- return None;
+ return std::nullopt;
auto &MF = *RootDef.getParent()->getParent();
if (GV->getPointerAlignment(MF.getDataLayout()) < Size)
- return None;
+ return std::nullopt;
unsigned OpFlags = STI.ClassifyGlobalReference(GV, MF.getTarget());
MachineIRBuilder MIRBuilder(RootDef);
@@ -6509,7 +6510,7 @@ AArch64InstructionSelector::selectAddrModeIndexed(MachineOperand &Root,
MachineRegisterInfo &MRI = MF.getRegInfo();
if (!Root.isReg())
- return None;
+ return std::nullopt;
MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
@@ -6552,7 +6553,7 @@ AArch64InstructionSelector::selectAddrModeIndexed(MachineOperand &Root,
// Before falling back to our general case, check if the unscaled
// instructions can handle this. If so, that's preferable.
if (selectAddrModeUnscaled(Root, Size))
- return None;
+ return std::nullopt;
return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
@@ -6583,7 +6584,7 @@ InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectShiftedRegister(MachineOperand &Root,
bool AllowROR) const {
if (!Root.isReg())
- return None;
+ return std::nullopt;
MachineRegisterInfo &MRI =
Root.getParent()->getParent()->getParent()->getRegInfo();
@@ -6592,17 +6593,17 @@ AArch64InstructionSelector::selectShiftedRegister(MachineOperand &Root,
MachineInstr *ShiftInst = MRI.getVRegDef(Root.getReg());
AArch64_AM::ShiftExtendType ShType = getShiftTypeForInst(*ShiftInst);
if (ShType == AArch64_AM::InvalidShiftExtend)
- return None;
+ return std::nullopt;
if (ShType == AArch64_AM::ROR && !AllowROR)
- return None;
+ return std::nullopt;
if (!isWorthFoldingIntoExtendedReg(*ShiftInst, MRI))
- return None;
+ return std::nullopt;
// Need an immediate on the RHS.
MachineOperand &ShiftRHS = ShiftInst->getOperand(2);
auto Immed = getImmedFromMO(ShiftRHS);
if (!Immed)
- return None;
+ return std::nullopt;
// We have something that we can fold. Fold in the shift's LHS and RHS into
// the instruction.
@@ -6698,7 +6699,7 @@ InstructionSelector::ComplexRendererFns
AArch64InstructionSelector::selectArithExtendedRegister(
MachineOperand &Root) const {
if (!Root.isReg())
- return None;
+ return std::nullopt;
MachineRegisterInfo &MRI =
Root.getParent()->getParent()->getParent()->getRegInfo();
@@ -6707,10 +6708,10 @@ AArch64InstructionSelector::selectArithExtendedRegister(
AArch64_AM::ShiftExtendType Ext;
MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI);
if (!RootDef)
- return None;
+ return std::nullopt;
if (!isWorthFoldingIntoExtendedReg(*RootDef, MRI))
- return None;
+ return std::nullopt;
// Check if we can fold a shift and an extend.
if (RootDef->getOpcode() == TargetOpcode::G_SHL) {
@@ -6718,24 +6719,24 @@ AArch64InstructionSelector::selectArithExtendedRegister(
MachineOperand &RHS = RootDef->getOperand(2);
Optional<uint64_t> MaybeShiftVal = getImmedFromMO(RHS);
if (!MaybeShiftVal)
- return None;
+ return std::nullopt;
ShiftVal = *MaybeShiftVal;
if (ShiftVal > 4)
- return None;
+ return std::nullopt;
// Look for a valid extend instruction on the LHS of the shift.
MachineOperand &LHS = RootDef->getOperand(1);
MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI);
if (!ExtDef)
- return None;
+ return std::nullopt;
Ext = getExtendTypeForInst(*ExtDef, MRI);
if (Ext == AArch64_AM::InvalidShiftExtend)
- return None;
+ return std::nullopt;
ExtReg = ExtDef->getOperand(1).getReg();
} else {
// Didn't get a shift. Try just folding an extend.
Ext = getExtendTypeForInst(*RootDef, MRI);
if (Ext == AArch64_AM::InvalidShiftExtend)
- return None;
+ return std::nullopt;
ExtReg = RootDef->getOperand(1).getReg();
// If we have a 32 bit instruction which zeroes out the high half of a
@@ -6745,7 +6746,7 @@ AArch64InstructionSelector::selectArithExtendedRegister(
if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) {
MachineInstr *ExtInst = MRI.getVRegDef(ExtReg);
if (isDef32(*ExtInst))
- return None;
+ return std::nullopt;
}
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 0842462f445bb..2b576b8085dd4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -117,7 +117,7 @@ static std::optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
// Look for the first non-undef element.
auto FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
if (FirstRealElt == M.end())
- return None;
+ return std::nullopt;
// Use APInt to handle overflow when calculating expected element.
unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
@@ -128,7 +128,7 @@ static std::optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
if (any_of(
make_range(std::next(FirstRealElt), M.end()),
[&ExpectedElt](int Elt) { return Elt != ExpectedElt++ && Elt >= 0; }))
- return None;
+ return std::nullopt;
// The index of an EXT is the first element if it is not UNDEF.
// Watch out for the beginning UNDEFs. The EXT index should be the expected
@@ -197,7 +197,7 @@ static bool isZipMask(ArrayRef<int> M, unsigned NumElts,
static std::optional<std::pair<bool, int>> isINSMask(ArrayRef<int> M,
int NumInputElements) {
if (M.size() != static_cast<size_t>(NumInputElements))
- return None;
+ return std::nullopt;
int NumLHSMatch = 0, NumRHSMatch = 0;
int LastLHSMismatch = -1, LastRHSMismatch = -1;
for (int Idx = 0; Idx < NumInputElements; ++Idx) {
@@ -214,7 +214,7 @@ static std::optional<std::pair<bool, int>> isINSMask(ArrayRef<int> M,
return std::make_pair(true, LastLHSMismatch);
if (NumRHSMatch == NumNeededToMatch)
return std::make_pair(false, LastRHSMismatch);
- return None;
+ return std::nullopt;
}
/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with a
@@ -563,7 +563,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
const MachineRegisterInfo &MRI) {
const auto &Ty = MRI.getType(RHS);
if (Ty.isVector())
- return None;
+ return std::nullopt;
unsigned Size = Ty.getSizeInBits();
assert((Size == 32 || Size == 64) && "Expected 32 or 64 bit compare only?");
@@ -571,16 +571,16 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// immediate, then there is nothing to change.
auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, MRI);
if (!ValAndVReg)
- return None;
+ return std::nullopt;
uint64_t C = ValAndVReg->Value.getZExtValue();
if (isLegalArithImmed(C))
- return None;
+ return std::nullopt;
// We have a non-arithmetic immediate. Check if adjusting the immediate and
// adjusting the predicate will result in a legal arithmetic immediate.
switch (P) {
default:
- return None;
+ return std::nullopt;
case CmpInst::ICMP_SLT:
case CmpInst::ICMP_SGE:
// Check for
@@ -591,7 +591,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// When c is not the smallest possible negative number.
if ((Size == 64 && static_cast<int64_t>(C) == INT64_MIN) ||
(Size == 32 && static_cast<int32_t>(C) == INT32_MIN))
- return None;
+ return std::nullopt;
P = (P == CmpInst::ICMP_SLT) ? CmpInst::ICMP_SLE : CmpInst::ICMP_SGT;
C -= 1;
break;
@@ -604,7 +604,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
//
// When c is not zero.
if (C == 0)
- return None;
+ return std::nullopt;
P = (P == CmpInst::ICMP_ULT) ? CmpInst::ICMP_ULE : CmpInst::ICMP_UGT;
C -= 1;
break;
@@ -618,7 +618,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// When c is not the largest possible signed integer.
if ((Size == 32 && static_cast<int32_t>(C) == INT32_MAX) ||
(Size == 64 && static_cast<int64_t>(C) == INT64_MAX))
- return None;
+ return std::nullopt;
P = (P == CmpInst::ICMP_SLE) ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGE;
C += 1;
break;
@@ -632,7 +632,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// When c is not the largest possible unsigned integer.
if ((Size == 32 && static_cast<uint32_t>(C) == UINT32_MAX) ||
(Size == 64 && C == UINT64_MAX))
- return None;
+ return std::nullopt;
P = (P == CmpInst::ICMP_ULE) ? CmpInst::ICMP_ULT : CmpInst::ICMP_UGE;
C += 1;
break;
@@ -643,7 +643,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
if (Size == 32)
C = static_cast<uint32_t>(C);
if (!isLegalArithImmed(C))
- return None;
+ return std::nullopt;
return {{C, P}};
}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index fb6c5af8f5fa3..e796aeb6bfc0c 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -332,7 +332,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
if (!TheTriple.isOSBinFormatELF())
- return None;
+ return std::nullopt;
unsigned Type = llvm::StringSwitch<unsigned>(Name)
#define ELF_RELOC(X, Y) .Case(#X, Y)
@@ -344,7 +344,7 @@ Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
.Case("BFD_RELOC_64", ELF::R_AARCH64_ABS64)
.Default(-1u);
if (Type == -1u)
- return None;
+ return std::nullopt;
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 9af526000e25a..2be5c62653e59 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -540,7 +540,7 @@ inline Optional<unsigned>
getSVEPredPatternFromNumElements(unsigned MinNumElts) {
switch (MinNumElts) {
default:
- return None;
+ return std::nullopt;
case 1:
case 2:
case 3:
@@ -849,7 +849,7 @@ AArch64StringToPACKeyID(StringRef Name) {
return AArch64PACKey::DA;
if (Name == "db")
return AArch64PACKey::DB;
- return None;
+ return std::nullopt;
}
namespace AArch64 {
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
index d4fe17ef36514..a3a9da8b8a8a4 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
+++ b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
@@ -55,19 +55,19 @@ Optional<bool> SMEAttrs::requiresSMChange(const SMEAttrs &Callee,
// and Callee has a streaming body, then we can ignore the interface of
// Callee.
if (BodyOverridesInterface && Callee.hasStreamingBody()) {
- return hasStreamingInterfaceOrBody() ? None : Optional<bool>(true);
+ return hasStreamingInterfaceOrBody() ? std::nullopt : Optional<bool>(true);
}
if (Callee.hasStreamingCompatibleInterface())
- return None;
+ return std::nullopt;
// Both non-streaming
if (hasNonStreamingInterfaceAndBody() && Callee.hasNonStreamingInterface())
- return None;
+ return std::nullopt;
// Both streaming
if (hasStreamingInterfaceOrBody() && Callee.hasStreamingInterface())
- return None;
+ return std::nullopt;
return Callee.hasStreamingInterface();
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index da145ed7563d5..a32fd52f55f6e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -518,7 +518,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
if (AllocSize == 0)
continue;
- MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : None;
+ MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : std::nullopt;
Align ABIAlign = DL.getValueOrABITypeAlignment(ParamAlign, ArgTy);
uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
index 2d210ecc051f8..159624892c4e0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
@@ -506,7 +506,7 @@ MetadataStreamerMsgPackV3::getAccessQualifier(StringRef AccQual) const {
.Case("read_only", StringRef("read_only"))
.Case("write_only", StringRef("write_only"))
.Case("read_write", StringRef("read_write"))
- .Default(None);
+ .Default(std::nullopt);
}
Optional<StringRef> MetadataStreamerMsgPackV3::getAddressSpaceQualifier(
@@ -525,7 +525,7 @@ Optional<StringRef> MetadataStreamerMsgPackV3::getAddressSpaceQualifier(
case AMDGPUAS::REGION_ADDRESS:
return StringRef("region");
default:
- return None;
+ return std::nullopt;
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
index 2d89692ac90e3..f9344a5fbecac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
@@ -98,7 +98,8 @@ class MetadataStreamerMsgPackV3 : public MetadataStreamer {
void emitKernelArg(const DataLayout &DL, Type *Ty, Align Alignment,
StringRef ValueKind, unsigned &Offset,
- msgpack::ArrayDocNode Args, MaybeAlign PointeeAlign = None,
+ msgpack::ArrayDocNode Args,
+ MaybeAlign PointeeAlign = std::nullopt,
StringRef Name = "", StringRef TypeName = "",
StringRef BaseTypeName = "", StringRef AccQual = "",
StringRef TypeQual = "");
@@ -191,7 +192,8 @@ class MetadataStreamerYamlV2 final : public MetadataStreamer {
void emitKernelArg(const Argument &Arg);
void emitKernelArg(const DataLayout &DL, Type *Ty, Align Alignment,
- ValueKind ValueKind, MaybeAlign PointeeAlign = None,
+ ValueKind ValueKind,
+ MaybeAlign PointeeAlign = std::nullopt,
StringRef Name = "", StringRef TypeName = "",
StringRef BaseTypeName = "", StringRef AccQual = "",
StringRef TypeQual = "");
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index ae0329f13b3aa..e4e297298f1cb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -1080,7 +1080,7 @@ void IGroupLPDAGMutation::addSchedBarrierEdges(SUnit &SchedBarrier) {
resetEdges(SchedBarrier, DAG);
auto InvertedMask =
invertSchedBarrierMask((SchedGroupMask)MI.getOperand(0).getImm());
- SchedGroup SG(InvertedMask, None, DAG, TII);
+ SchedGroup SG(InvertedMask, std::nullopt, DAG, TII);
SG.initSchedGroup();
// Preserve original instruction ordering relative to the SCHED_BARRIER.
SG.link(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index e7fb4a76b6a29..bff43cbf82961 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1029,7 +1029,7 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
Type *BaseArgTy = Arg.getType();
Type *MemArgTy = IsByRef ? Arg.getParamByRefType() : BaseArgTy;
Align Alignment = DL.getValueOrABITypeAlignment(
- IsByRef ? Arg.getParamAlign() : None, MemArgTy);
+ IsByRef ? Arg.getParamAlign() : std::nullopt, MemArgTy);
MaxAlign = std::max(Alignment, MaxAlign);
uint64_t AllocSize = DL.getTypeAllocSize(MemArgTy);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index e5da2ebc975d7..38808b536c2f8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -270,7 +270,7 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
if (!canSafelyConvertTo16Bit(*Coord, HasSampler)) {
if (OperandIndex < ImageDimIntr->CoordStart ||
ImageDimIntr->GradientStart == ImageDimIntr->CoordStart) {
- return None;
+ return std::nullopt;
}
// All gradients can be converted, so convert only them
OnlyDerivatives = true;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index e65178b95b6e9..3f6afb080decd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3727,7 +3727,7 @@ AMDGPUInstructionSelector::selectVOP3Mods_nnan(MachineOperand &Root) const {
unsigned Mods;
std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
if (!isKnownNeverNaN(Src, *MRI))
- return None;
+ return std::nullopt;
return {{
[=](MachineInstrBuilder &MIB) {
@@ -3856,7 +3856,7 @@ AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const {
Register Base;
int64_t Offset;
if (!selectSmrdOffset(Root, Base, /* SOffset= */ nullptr, &Offset))
- return None;
+ return std::nullopt;
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}};
@@ -3868,14 +3868,14 @@ AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const {
getAddrModeInfo(*Root.getParent(), *MRI, AddrInfo);
if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
- return None;
+ return std::nullopt;
const GEPInfo &GEPInfo = AddrInfo[0];
Register PtrReg = GEPInfo.SgprParts[0];
Optional<int64_t> EncodedImm =
AMDGPU::getSMRDEncodedLiteralOffset32(STI, GEPInfo.Imm);
if (!EncodedImm)
- return None;
+ return std::nullopt;
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
@@ -3887,7 +3887,7 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const {
Register Base, SOffset;
if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr))
- return None;
+ return std::nullopt;
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};
@@ -3898,7 +3898,7 @@ AMDGPUInstructionSelector::selectSmrdSgprImm(MachineOperand &Root) const {
Register Base, SOffset;
int64_t Offset;
if (!selectSmrdOffset(Root, Base, &SOffset, &Offset))
- return None;
+ return std::nullopt;
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
@@ -4018,7 +4018,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
!TII.isInlineConstant(APInt(32, ConstOffset & 0xffffffff)) +
!TII.isInlineConstant(APInt(32, ConstOffset >> 32));
if (STI.getConstantBusLimit(AMDGPU::V_ADD_U32_e64) > NumLiterals)
- return None;
+ return std::nullopt;
}
}
}
@@ -4053,7 +4053,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
// drop this.
if (AddrDef->MI->getOpcode() == AMDGPU::G_IMPLICIT_DEF ||
AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg))
- return None;
+ return std::nullopt;
// It's cheaper to materialize a single 32-bit zero for vaddr than the two
// moves required to copy a 64-bit SGPR to VGPR.
@@ -4121,7 +4121,7 @@ AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const {
}
if (!isSGPR(SAddr))
- return None;
+ return std::nullopt;
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr
@@ -4166,17 +4166,17 @@ AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const {
auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
if (AddrDef->MI->getOpcode() != AMDGPU::G_PTR_ADD)
- return None;
+ return std::nullopt;
Register RHS = AddrDef->MI->getOperand(2).getReg();
if (RBI.getRegBank(RHS, *MRI, TRI)->getID() != AMDGPU::VGPRRegBankID)
- return None;
+ return std::nullopt;
Register LHS = AddrDef->MI->getOperand(1).getReg();
auto LHSDef = getDefSrcRegIgnoringCopies(LHS, *MRI);
if (checkFlatScratchSVSSwizzleBug(RHS, LHS, ImmOffset))
- return None;
+ return std::nullopt;
if (LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
int FI = LHSDef->MI->getOperand(1).getIndex();
@@ -4188,7 +4188,7 @@ AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const {
}
if (!isSGPR(LHS))
- return None;
+ return std::nullopt;
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr
@@ -4825,7 +4825,7 @@ static Optional<uint64_t> getConstantZext32Val(Register Reg,
// getIConstantVRegVal sexts any values, so see if that matters.
Optional<int64_t> OffsetVal = getIConstantVRegSExtVal(Reg, MRI);
if (!OffsetVal || !isInt<32>(*OffsetVal))
- return None;
+ return std::nullopt;
return Lo_32(*OffsetVal);
}
@@ -4868,12 +4868,12 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
std::tie(SOffset, Offset) =
AMDGPU::getBaseWithConstantOffset(*MRI, Root.getReg(), KnownBits);
if (!SOffset)
- return None;
+ return std::nullopt;
Optional<int64_t> EncodedOffset =
AMDGPU::getSMRDEncodedOffset(STI, Offset, /* IsBuffer */ true);
if (!EncodedOffset)
- return None;
+ return std::nullopt;
assert(MRI->getType(SOffset) == LLT::scalar(32));
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
index 2e5c35f1f5710..bacd12b919b61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
@@ -92,7 +92,7 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
for (Argument &Arg : F.args()) {
const bool IsByRef = Arg.hasByRefAttr();
Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
- MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : None;
+ MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : std::nullopt;
Align ABITypeAlign = DL.getValueOrABITypeAlignment(ParamAlign, ArgTy);
uint64_t Size = DL.getTypeSizeInBits(ArgTy);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
index 745734aac2b43..3a23b712da9f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h
@@ -65,7 +65,7 @@ class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF {
SSID == getSystemOneAddressSpaceSSID())
return 4;
- return None;
+ return std::nullopt;
}
/// \returns True if \p SSID is restricted to single address space, false
@@ -126,7 +126,7 @@ class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF {
const auto &AIO = getSyncScopeInclusionOrdering(A);
const auto &BIO = getSyncScopeInclusionOrdering(B);
if (!AIO || !BIO)
- return None;
+ return std::nullopt;
bool IsAOneAddressSpace = isOneAddressSpace(A);
bool IsBOneAddressSpace = isOneAddressSpace(B);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
index 1ba7beddbd100..f514f7919188d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -282,7 +282,7 @@ AMDGPUPromoteAllocaImpl::getLocalSizeYZ(IRBuilder<> &Builder) {
Value *GEPZU = Builder.CreateConstInBoundsGEP1_64(I32Ty, CastDispatchPtr, 2);
LoadInst *LoadZU = Builder.CreateAlignedLoad(I32Ty, GEPZU, Align(4));
- MDNode *MD = MDNode::get(Mod->getContext(), None);
+ MDNode *MD = MDNode::get(Mod->getContext(), std::nullopt);
LoadXY->setMetadata(LLVMContext::MD_invariant_load, MD);
LoadZU->setMetadata(LLVMContext::MD_invariant_load, MD);
ST.makeLIDRangeMetadata(LoadZU);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp
index 965b309a25f7b..b7521540c0205 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp
@@ -62,7 +62,7 @@ class AMDGPUReleaseVGPRs : public MachineFunctionPass {
return false;
}
// Wait until the values are propagated from the predecessors
- return None;
+ return std::nullopt;
}
public:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index e33f5d079915b..b7d19501ee7b5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -540,7 +540,7 @@ uint64_t AMDGPUSubtarget::getExplicitKernArgSize(const Function &F,
const bool IsByRef = Arg.hasByRefAttr();
Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
Align Alignment = DL.getValueOrABITypeAlignment(
- IsByRef ? Arg.getParamAlign() : None, ArgTy);
+ IsByRef ? Arg.getParamAlign() : std::nullopt, ArgTy);
uint64_t AllocSize = DL.getTypeAllocSize(ArgTy);
ExplicitArgBytes = alignTo(ExplicitArgBytes, Alignment) + AllocSize;
MaxAlign = std::max(MaxAlign, Alignment);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 0cecf95c007d0..a801279c44a10 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1451,7 +1451,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
RegName.Value.size(), SourceMgr::DK_Error,
"incorrect register class for field", RegName.Value,
- None, None);
+ std::nullopt, std::nullopt);
SourceRange = RegName.SourceRange;
return true;
};
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index d9632097a247d..347ce87acd264 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -203,7 +203,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
bool areInlineCompatible(const Function *Caller,
const Function *Callee) const;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 617b5bb2d859f..1fff896c10a8f 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2888,7 +2888,7 @@ AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {
case IS_SGPR:
return StringRef(".amdgcn.next_free_sgpr");
default:
- return None;
+ return std::nullopt;
}
}
@@ -4092,7 +4092,7 @@ Optional<StringRef> AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
// with 9-bit operands only. Ignore encodings which do not accept these.
const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA;
if ((Desc.TSFlags & Enc) == 0)
- return None;
+ return std::nullopt;
for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {
auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);
@@ -4112,7 +4112,7 @@ Optional<StringRef> AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
}
}
- return None;
+ return std::nullopt;
}
SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 8cffbd973317f..089a02ff268b4 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2232,7 +2232,7 @@ AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
Size = 64; // Size = 64 regardless of success or failure.
return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
}
- return None;
+ return std::nullopt;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index bda3c25e956bd..79d025e8010f7 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -168,7 +168,7 @@ Optional<MCFixupKind> AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
.Case(#Name, MCFixupKind(FirstLiteralRelocationKind + Value))
#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
#undef ELF_RELOC
- .Default(None);
+ .Default(std::nullopt);
}
const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
index 2bb9c4a6396b2..030af8a7161b3 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
@@ -105,13 +105,13 @@ class AMDGPUTargetStreamer : public MCTargetStreamer {
return TargetID;
}
void initializeTargetID(const MCSubtargetInfo &STI) {
- assert(TargetID == None && "TargetID can only be initialized once");
+ assert(TargetID == std::nullopt && "TargetID can only be initialized once");
TargetID.emplace(STI);
}
void initializeTargetID(const MCSubtargetInfo &STI, StringRef FeatureString) {
initializeTargetID(STI);
- assert(getTargetID() != None && "TargetID is None");
+ assert(getTargetID() != std::nullopt && "TargetID is None");
getTargetID()->setTargetIDFromFeaturesString(FeatureString);
}
};
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index b38a73832e0a0..214a16f9ce4a5 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -1989,12 +1989,12 @@ SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
return Op.getImm();
if (!Op.isReg())
- return None;
+ return std::nullopt;
MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 ||
!Def->getOperand(1).isImm())
- return None;
+ return std::nullopt;
return Def->getOperand(1).getImm();
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index d17d86f40680a..75ec15ff5c355 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -587,7 +587,7 @@ convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
if (Any)
return AI;
- return None;
+ return std::nullopt;
}
yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
@@ -651,13 +651,13 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
SourceMgr::DK_Error, toString(FIOrErr.takeError()),
- "", None, None);
+ "", std::nullopt, std::nullopt);
SourceRange = YamlMFI.ScavengeFI->SourceRange;
return true;
}
ScavengeFI = *FIOrErr;
} else {
- ScavengeFI = None;
+ ScavengeFI = std::nullopt;
}
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index b4d812df74380..65d95e54fe414 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -664,7 +664,7 @@ SIMemOpAccess::toSIAtomicScope(SyncScope::ID SSID,
return std::make_tuple(SIAtomicScope::SINGLETHREAD,
SIAtomicAddrSpace::ATOMIC & InstrAddrSpace,
false);
- return None;
+ return std::nullopt;
}
SIAtomicAddrSpace SIMemOpAccess::toSIAtomicAddrSpace(unsigned AS) const {
@@ -711,7 +711,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
if (!IsSyncScopeInclusion) {
reportUnsupported(MI,
"Unsupported non-inclusive atomic synchronization scope");
- return None;
+ return std::nullopt;
}
SSID = *IsSyncScopeInclusion ? SSID : MMO->getSyncScopeID();
@@ -730,7 +730,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
auto ScopeOrNone = toSIAtomicScope(SSID, InstrAddrSpace);
if (!ScopeOrNone) {
reportUnsupported(MI, "Unsupported atomic synchronization scope");
- return None;
+ return std::nullopt;
}
std::tie(Scope, OrderingAddrSpace, IsCrossAddressSpaceOrdering) =
*ScopeOrNone;
@@ -738,7 +738,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace) ||
((InstrAddrSpace & SIAtomicAddrSpace::ATOMIC) == SIAtomicAddrSpace::NONE)) {
reportUnsupported(MI, "Unsupported atomic address space");
- return None;
+ return std::nullopt;
}
}
return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, InstrAddrSpace,
@@ -751,7 +751,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getLoadInfo(
assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
if (!(MI->mayLoad() && !MI->mayStore()))
- return None;
+ return std::nullopt;
// Be conservative if there are no memory operands.
if (MI->getNumMemOperands() == 0)
@@ -765,7 +765,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getStoreInfo(
assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
if (!(!MI->mayLoad() && MI->mayStore()))
- return None;
+ return std::nullopt;
// Be conservative if there are no memory operands.
if (MI->getNumMemOperands() == 0)
@@ -779,7 +779,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo(
assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE)
- return None;
+ return std::nullopt;
AtomicOrdering Ordering =
static_cast<AtomicOrdering>(MI->getOperand(0).getImm());
@@ -788,7 +788,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo(
auto ScopeOrNone = toSIAtomicScope(SSID, SIAtomicAddrSpace::ATOMIC);
if (!ScopeOrNone) {
reportUnsupported(MI, "Unsupported atomic synchronization scope");
- return None;
+ return std::nullopt;
}
SIAtomicScope Scope = SIAtomicScope::NONE;
@@ -800,7 +800,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo(
if ((OrderingAddrSpace == SIAtomicAddrSpace::NONE) ||
((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace)) {
reportUnsupported(MI, "Unsupported atomic address space");
- return None;
+ return std::nullopt;
}
return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, SIAtomicAddrSpace::ATOMIC,
@@ -812,7 +812,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicCmpxchgOrRmwInfo(
assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
if (!(MI->mayLoad() && MI->mayStore()))
- return None;
+ return std::nullopt;
// Be conservative if there are no memory operands.
if (MI->getNumMemOperands() == 0)
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
index 006760fb76466..037e0ecaf37f8 100644
--- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -504,17 +504,17 @@ Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const {
const MachineInstr *DefInst = Def.getParent();
if (!TII->isFoldableCopy(*DefInst))
- return None;
+ return std::nullopt;
const MachineOperand &Copied = DefInst->getOperand(1);
if (!Copied.isImm())
- return None;
+ return std::nullopt;
return Copied.getImm();
}
}
- return None;
+ return std::nullopt;
}
std::unique_ptr<SDWAOperand>
@@ -697,19 +697,19 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
auto CheckOROperandsForSDWA =
[&](const MachineOperand *Op1, const MachineOperand *Op2) -> CheckRetType {
if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg())
- return CheckRetType(None);
+ return CheckRetType(std::nullopt);
MachineOperand *Op1Def = findSingleRegDef(Op1, MRI);
if (!Op1Def)
- return CheckRetType(None);
+ return CheckRetType(std::nullopt);
MachineInstr *Op1Inst = Op1Def->getParent();
if (!TII->isSDWA(*Op1Inst))
- return CheckRetType(None);
+ return CheckRetType(std::nullopt);
MachineOperand *Op2Def = findSingleRegDef(Op2, MRI);
if (!Op2Def)
- return CheckRetType(None);
+ return CheckRetType(std::nullopt);
return CheckRetType(std::make_pair(Op1Def, Op2Def));
};
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index ce2f7f0642be1..2a5834c64d2fa 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -100,7 +100,7 @@ namespace AMDGPU {
Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI) {
if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
- return None;
+ return std::nullopt;
switch (AmdhsaCodeObjectVersion) {
case 2:
@@ -2441,25 +2441,26 @@ Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
// The signed version is always a byte offset.
if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
assert(hasSMEMByteOffset(ST));
- return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : None;
+ return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : std::nullopt;
}
if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
- return None;
+ return std::nullopt;
int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
? Optional<int64_t>(EncodedOffset)
- : None;
+ : std::nullopt;
}
Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
int64_t ByteOffset) {
if (!isCI(ST) || !isDwordAligned(ByteOffset))
- return None;
+ return std::nullopt;
int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
- return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
+ return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset)
+ : std::nullopt;
}
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 5e38a0c731e6b..24ec9b2e3655c 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -262,15 +262,17 @@ unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
///
/// For subtargets which support it, \p EnableWavefrontSize32 should match
/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
-unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
- Optional<bool> EnableWavefrontSize32 = None);
+unsigned
+getVGPRAllocGranule(const MCSubtargetInfo *STI,
+ Optional<bool> EnableWavefrontSize32 = std::nullopt);
/// \returns VGPR encoding granularity for given subtarget \p STI.
///
/// For subtargets which support it, \p EnableWavefrontSize32 should match
/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
-unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
- Optional<bool> EnableWavefrontSize32 = None);
+unsigned
+getVGPREncodingGranule(const MCSubtargetInfo *STI,
+ Optional<bool> EnableWavefrontSize32 = std::nullopt);
/// \returns Total number of VGPRs for given subtarget \p STI.
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
@@ -292,7 +294,7 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
/// For subtargets which support it, \p EnableWavefrontSize32 should match the
/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
- Optional<bool> EnableWavefrontSize32 = None);
+ Optional<bool> EnableWavefrontSize32 = std::nullopt);
} // end namespace IsaInfo
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index a5a5b73561547..e87825e50ad04 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1065,7 +1065,7 @@ ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
if (!MI.isMoveReg() ||
(MI.getOpcode() == ARM::VORRq &&
MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
- return None;
+ return std::nullopt;
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
}
@@ -1094,7 +1094,7 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
// We need to produce a fragment description (the call site value of s1 is
// /not/ just d8).
if (DstReg != Reg)
- return None;
+ return std::nullopt;
}
return TargetInstrInfo::describeLoadedValue(MI, Reg);
}
@@ -5565,19 +5565,19 @@ Optional<RegImmPair> ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
// destination register.
const MachineOperand &Op0 = MI.getOperand(0);
if (!Op0.isReg() || Reg != Op0.getReg())
- return None;
+ return std::nullopt;
// We describe SUBri or ADDri instructions.
if (Opcode == ARM::SUBri)
Sign = -1;
else if (Opcode != ARM::ADDri)
- return None;
+ return std::nullopt;
// TODO: Third operand can be global address (usually some string). Since
// strings can be relocated we cannot calculate their offsets for
// now.
if (!MI.getOperand(1).isReg() || !MI.getOperand(2).isImm())
- return None;
+ return std::nullopt;
Offset = MI.getOperand(2).getImm() * Sign;
return RegImmPair{MI.getOperand(1).getReg(), Offset};
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 5f04ded7b10f3..a290903b5980a 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -188,10 +188,10 @@ class ARMFastISel final : public FastISel {
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt);
bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
- MaybeAlign Alignment = None, bool isZExt = true,
+ MaybeAlign Alignment = std::nullopt, bool isZExt = true,
bool allocReg = true);
bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
- MaybeAlign Alignment = None);
+ MaybeAlign Alignment = std::nullopt);
bool ARMComputeAddress(const Value *Obj, Address &Addr);
void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
bool ARMIsMemCpySmall(uint64_t Len);
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 5a257d25179e3..ab8bb810f7333 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -3536,7 +3536,7 @@ getContiguousRangeOfSetBits(const APInt &A) {
unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
unsigned LastOne = A.countTrailingZeros();
if (A.countPopulation() != (FirstOne - LastOne + 1))
- return None;
+ return std::nullopt;
return std::make_pair(FirstOne, LastOne);
}
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index e919b9b2aee84..db96c3da54cf7 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -216,7 +216,7 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
bool preferInLoopReduction(unsigned Opcode, Type *Ty,
TTI::ReductionFlags Flags) const;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index cdecb656aad0a..b06e89f0ed9f1 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -429,15 +429,15 @@ class ARMAsmParser : public MCTargetAsmParser {
VPTState.CurPosition = ~0U;
}
- void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ void Note(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
return getParser().Note(L, Msg, Range);
}
- bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ bool Warning(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
return getParser().Warning(L, Msg, Range);
}
- bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
+ bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
return getParser().Error(L, Msg, Range);
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index e8032c376f60a..673a00920e813 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -48,7 +48,7 @@ class ARMELFObjectWriter : public MCELFObjectTargetWriter {
} // end anonymous namespace
Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
- return None;
+ return std::nullopt;
}
Optional<MCFixupKind> ARMAsmBackendELF::getFixupKind(StringRef Name) const {
@@ -62,7 +62,7 @@ Optional<MCFixupKind> ARMAsmBackendELF::getFixupKind(StringRef Name) const {
.Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
.Default(-1u);
if (Type == -1u)
- return None;
+ return std::nullopt;
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 9f85d72cc8101..dbaf36e712c6b 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -444,12 +444,12 @@ static Optional<uint64_t>
evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
unsigned MemOpIndex, uint64_t Addr) {
if (MemOpIndex + 1 >= Desc.getNumOperands())
- return None;
+ return std::nullopt;
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
- return None;
+ return std::nullopt;
int32_t OffImm = (int32_t)MO2.getImm();
// Special value for #-0. All others are normal.
@@ -463,13 +463,13 @@ static Optional<uint64_t> evaluateMemOpAddrForAddrMode3(const MCInst &Inst,
unsigned MemOpIndex,
uint64_t Addr) {
if (MemOpIndex + 2 >= Desc.getNumOperands())
- return None;
+ return std::nullopt;
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
- return None;
+ return std::nullopt;
unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm());
@@ -484,12 +484,12 @@ static Optional<uint64_t> evaluateMemOpAddrForAddrMode5(const MCInst &Inst,
unsigned MemOpIndex,
uint64_t Addr) {
if (MemOpIndex + 1 >= Desc.getNumOperands())
- return None;
+ return std::nullopt;
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
- return None;
+ return std::nullopt;
unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
@@ -503,12 +503,12 @@ static Optional<uint64_t>
evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc,
unsigned MemOpIndex, uint64_t Addr) {
if (MemOpIndex + 1 >= Desc.getNumOperands())
- return None;
+ return std::nullopt;
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
- return None;
+ return std::nullopt;
unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm());
@@ -523,12 +523,12 @@ static Optional<uint64_t>
evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
unsigned MemOpIndex, uint64_t Addr) {
if (MemOpIndex + 1 >= Desc.getNumOperands())
- return None;
+ return std::nullopt;
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
- return None;
+ return std::nullopt;
int32_t OffImm = (int32_t)MO2.getImm();
assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
@@ -545,7 +545,7 @@ evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
unsigned MemOpIndex, uint64_t Addr) {
const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
if (!MO1.isImm())
- return None;
+ return std::nullopt;
int32_t OffImm = (int32_t)MO1.getImm();
@@ -569,14 +569,14 @@ Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
// Only load instructions can have PC-relative memory addressing.
if (!Desc.mayLoad())
- return None;
+ return std::nullopt;
// PC-relative addressing does not update the base register.
uint64_t TSFlags = Desc.TSFlags;
unsigned IndexMode =
(TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
if (IndexMode != ARMII::IndexModeNone)
- return None;
+ return std::nullopt;
// Find the memory addressing operand in the instruction.
unsigned OpIndex = Desc.NumDefs;
@@ -584,7 +584,7 @@ Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
Desc.OpInfo[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
++OpIndex;
if (OpIndex == Desc.getNumOperands())
- return None;
+ return std::nullopt;
// Base address for PC-relative addressing is always 32-bit aligned.
Addr &= ~0x3;
@@ -609,7 +609,7 @@ Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
switch (AddrMode) {
default:
- return None;
+ return std::nullopt;
case ARMII::AddrMode_i12:
return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
case ARMII::AddrMode3:
diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h
index 6a255b7316396..8eb6ee1ca497f 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepArch.h
+++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h
@@ -46,7 +46,7 @@ inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
.Case("hexagonv71", Hexagon::ArchEnum::V71)
.Case("hexagonv71t", Hexagon::ArchEnum::V71)
.Case("hexagonv73", Hexagon::ArchEnum::V73)
- .Default(None);
+ .Default(std::nullopt);
}
} // namespace Hexagon
} // namespace llvm
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 1e36e641991e0..c978dcd978a9b 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1018,7 +1018,7 @@ findCFILocation(MachineBasicBlock &B) {
if (HasAllocFrame)
return HasCall ? It : std::next(It);
}
- return None;
+ return std::nullopt;
}
void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
index 98d315c8fcde8..49d9520b8323e 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
@@ -129,7 +129,7 @@ class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
Type *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
const Value *Ptr, bool VariableMask,
Align Alignment,
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 2e350cd86d6fd..279ff739cca6e 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -126,7 +126,7 @@ class HexagonVectorCombine {
Value *createHvxIntrinsic(IRBuilderBase &Builder, Intrinsic::ID IntID,
Type *RetTy, ArrayRef<Value *> Args,
- ArrayRef<Type *> ArgTys = None) const;
+ ArrayRef<Type *> ArgTys = std::nullopt) const;
SmallVector<Value *> splitVectorElements(IRBuilderBase &Builder, Value *Vec,
unsigned ToWidth) const;
Value *joinVectorElements(IRBuilderBase &Builder, ArrayRef<Value *> Values,
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index 02d0e770ba66b..222d7acce3226 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -100,7 +100,7 @@ Optional<DestSourcePair>
Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
if (MI.isMoveReg())
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
- return None;
+ return std::nullopt;
}
void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 191accb359393..dd0b384ff53d5 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -786,7 +786,7 @@ void MipsAsmPrinter::emitStartOfAsmFile(Module &M) {
StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
StringRef FS = TM.getTargetFeatureString();
const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
- const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, None);
+ const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, std::nullopt);
bool IsABICalls = STI.isABICalls();
const MipsABIInfo &ABI = MTM.getABI();
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 3c3700fbb5c27..a7b1bcf9c20fa 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -956,7 +956,7 @@ MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
// TODO: Handle cases where the Reg is sub- or super-register of the
// DestReg.
if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
- return None;
+ return std::nullopt;
}
return TargetInstrInfo::describeLoadedValue(MI, Reg);
@@ -968,7 +968,7 @@ Optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
// destination register.
const MachineOperand &Op0 = MI.getOperand(0);
if (!Op0.isReg() || Reg != Op0.getReg())
- return None;
+ return std::nullopt;
switch (MI.getOpcode()) {
case Mips::ADDiu:
@@ -983,5 +983,5 @@ Optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
// TODO: Handle case where Sop1 is a frame-index.
}
}
- return None;
+ return std::nullopt;
}
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 26b31cfa9f2a8..4c93a51358cee 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -228,7 +228,7 @@ MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
// from copyPhysReg function.
if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
- return None;
+ return std::nullopt;
else if (isDSPControlWrite) {
return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
@@ -238,7 +238,7 @@ MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
} else if (MI.isMoveReg() || isORCopyInst(MI)) {
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
}
- return None;
+ return std::nullopt;
}
void MipsSEInstrInfo::
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index fb0aa397d393c..fa970512eb495 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -128,11 +128,12 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
getEffectiveCodeModel(CM, CodeModel::Small), OL),
isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
- Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None),
+ Subtarget(nullptr),
+ DefaultSubtarget(TT, CPU, FS, isLittle, *this, std::nullopt),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
- isLittle, *this, None),
+ isLittle, *this, std::nullopt),
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
- isLittle, *this, None) {
+ isLittle, *this, std::nullopt) {
Subtarget = &DefaultSubtarget;
initAsmInfo();
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 3c0b9c506c996..fb71c739b085f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -833,7 +833,7 @@ static Optional<unsigned> pickOpcodeForVT(
case MVT::f64:
return Opcode_f64;
default:
- return None;
+ return std::nullopt;
}
}
@@ -1087,11 +1087,11 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
NVPTX::LDV_f32_v2_avar, NVPTX::LDV_f64_v2_avar);
break;
case NVPTXISD::LoadV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar,
- NVPTX::LDV_i16_v4_avar, NVPTX::LDV_i32_v4_avar, None,
- NVPTX::LDV_f16_v4_avar, NVPTX::LDV_f16x2_v4_avar,
- NVPTX::LDV_f32_v4_avar, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::LDV_i8_v4_avar, NVPTX::LDV_i16_v4_avar,
+ NVPTX::LDV_i32_v4_avar, std::nullopt,
+ NVPTX::LDV_f16_v4_avar, NVPTX::LDV_f16x2_v4_avar,
+ NVPTX::LDV_f32_v4_avar, std::nullopt);
break;
}
if (!Opcode)
@@ -1114,11 +1114,11 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
NVPTX::LDV_f32_v2_asi, NVPTX::LDV_f64_v2_asi);
break;
case NVPTXISD::LoadV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_asi,
- NVPTX::LDV_i16_v4_asi, NVPTX::LDV_i32_v4_asi, None,
- NVPTX::LDV_f16_v4_asi, NVPTX::LDV_f16x2_v4_asi,
- NVPTX::LDV_f32_v4_asi, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::LDV_i8_v4_asi, NVPTX::LDV_i16_v4_asi,
+ NVPTX::LDV_i32_v4_asi, std::nullopt,
+ NVPTX::LDV_f16_v4_asi, NVPTX::LDV_f16x2_v4_asi,
+ NVPTX::LDV_f32_v4_asi, std::nullopt);
break;
}
if (!Opcode)
@@ -1145,9 +1145,9 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
case NVPTXISD::LoadV4:
Opcode = pickOpcodeForVT(
EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64,
- NVPTX::LDV_i16_v4_ari_64, NVPTX::LDV_i32_v4_ari_64, None,
+ NVPTX::LDV_i16_v4_ari_64, NVPTX::LDV_i32_v4_ari_64, std::nullopt,
NVPTX::LDV_f16_v4_ari_64, NVPTX::LDV_f16x2_v4_ari_64,
- NVPTX::LDV_f32_v4_ari_64, None);
+ NVPTX::LDV_f32_v4_ari_64, std::nullopt);
break;
}
} else {
@@ -1162,11 +1162,11 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
NVPTX::LDV_f32_v2_ari, NVPTX::LDV_f64_v2_ari);
break;
case NVPTXISD::LoadV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari,
- NVPTX::LDV_i16_v4_ari, NVPTX::LDV_i32_v4_ari, None,
- NVPTX::LDV_f16_v4_ari, NVPTX::LDV_f16x2_v4_ari,
- NVPTX::LDV_f32_v4_ari, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::LDV_i8_v4_ari, NVPTX::LDV_i16_v4_ari,
+ NVPTX::LDV_i32_v4_ari, std::nullopt,
+ NVPTX::LDV_f16_v4_ari, NVPTX::LDV_f16x2_v4_ari,
+ NVPTX::LDV_f32_v4_ari, std::nullopt);
break;
}
}
@@ -1193,9 +1193,9 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
case NVPTXISD::LoadV4:
Opcode = pickOpcodeForVT(
EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg_64,
- NVPTX::LDV_i16_v4_areg_64, NVPTX::LDV_i32_v4_areg_64, None,
+ NVPTX::LDV_i16_v4_areg_64, NVPTX::LDV_i32_v4_areg_64, std::nullopt,
NVPTX::LDV_f16_v4_areg_64, NVPTX::LDV_f16x2_v4_areg_64,
- NVPTX::LDV_f32_v4_areg_64, None);
+ NVPTX::LDV_f32_v4_areg_64, std::nullopt);
break;
}
} else {
@@ -1213,9 +1213,9 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
case NVPTXISD::LoadV4:
Opcode = pickOpcodeForVT(
EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_areg,
- NVPTX::LDV_i16_v4_areg, NVPTX::LDV_i32_v4_areg, None,
+ NVPTX::LDV_i16_v4_areg, NVPTX::LDV_i32_v4_areg, std::nullopt,
NVPTX::LDV_f16_v4_areg, NVPTX::LDV_f16x2_v4_areg,
- NVPTX::LDV_f32_v4_areg, None);
+ NVPTX::LDV_f32_v4_areg, std::nullopt);
break;
}
}
@@ -1347,22 +1347,22 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
break;
case NVPTXISD::LoadV4:
case NVPTXISD::LDGV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar, None,
- NVPTX::INT_PTX_LDG_G_v4f16_ELE_avar,
- NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_avar,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar,
+ NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar,
+ NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar, std::nullopt,
+ NVPTX::INT_PTX_LDG_G_v4f16_ELE_avar,
+ NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_avar,
+ NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar, std::nullopt);
break;
case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar, None,
- NVPTX::INT_PTX_LDU_G_v4f16_ELE_avar,
- NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_avar,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar,
+ NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar,
+ NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar, std::nullopt,
+ NVPTX::INT_PTX_LDU_G_v4f16_ELE_avar,
+ NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_avar,
+ NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar, std::nullopt);
break;
}
if (!Opcode)
@@ -1423,22 +1423,22 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
break;
case NVPTXISD::LoadV4:
case NVPTXISD::LDGV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64, None,
- NVPTX::INT_PTX_LDG_G_v4f16_ELE_ari64,
- NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_ari64,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64,
+ NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64,
+ NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64, std::nullopt,
+ NVPTX::INT_PTX_LDG_G_v4f16_ELE_ari64,
+ NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_ari64,
+ NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64, std::nullopt);
break;
case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64, None,
- NVPTX::INT_PTX_LDU_G_v4f16_ELE_ari64,
- NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_ari64,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64,
+ NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64,
+ NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64, std::nullopt,
+ NVPTX::INT_PTX_LDU_G_v4f16_ELE_ari64,
+ NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_ari64,
+ NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64, std::nullopt);
break;
}
} else {
@@ -1493,22 +1493,22 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
break;
case NVPTXISD::LoadV4:
case NVPTXISD::LDGV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32, None,
- NVPTX::INT_PTX_LDG_G_v4f16_ELE_ari32,
- NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_ari32,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32,
+ NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32,
+ NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32, std::nullopt,
+ NVPTX::INT_PTX_LDG_G_v4f16_ELE_ari32,
+ NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_ari32,
+ NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32, std::nullopt);
break;
case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32, None,
- NVPTX::INT_PTX_LDU_G_v4f16_ELE_ari32,
- NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_ari32,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32,
+ NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32,
+ NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32, std::nullopt,
+ NVPTX::INT_PTX_LDU_G_v4f16_ELE_ari32,
+ NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_ari32,
+ NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32, std::nullopt);
break;
}
}
@@ -1569,22 +1569,22 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
break;
case NVPTXISD::LoadV4:
case NVPTXISD::LDGV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64, None,
- NVPTX::INT_PTX_LDG_G_v4f16_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_areg64,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64,
+ NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64,
+ NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64, std::nullopt,
+ NVPTX::INT_PTX_LDG_G_v4f16_ELE_areg64,
+ NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_areg64,
+ NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64, std::nullopt);
break;
case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64, None,
- NVPTX::INT_PTX_LDU_G_v4f16_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_areg64,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64,
+ NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64,
+ NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64, std::nullopt,
+ NVPTX::INT_PTX_LDU_G_v4f16_ELE_areg64,
+ NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_areg64,
+ NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64, std::nullopt);
break;
}
} else {
@@ -1639,22 +1639,22 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
break;
case NVPTXISD::LoadV4:
case NVPTXISD::LDGV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32, None,
- NVPTX::INT_PTX_LDG_G_v4f16_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_areg32,
- NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32,
+ NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32,
+ NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32, std::nullopt,
+ NVPTX::INT_PTX_LDG_G_v4f16_ELE_areg32,
+ NVPTX::INT_PTX_LDG_G_v4f16x2_ELE_areg32,
+ NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32, std::nullopt);
break;
case NVPTXISD::LDUV4:
- Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
- NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32, None,
- NVPTX::INT_PTX_LDU_G_v4f16_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_areg32,
- NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32,
+ NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32,
+ NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32, std::nullopt,
+ NVPTX::INT_PTX_LDU_G_v4f16_ELE_areg32,
+ NVPTX::INT_PTX_LDU_G_v4f16x2_ELE_areg32,
+ NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32, std::nullopt);
break;
}
}
@@ -1955,11 +1955,11 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
NVPTX::STV_f32_v2_avar, NVPTX::STV_f64_v2_avar);
break;
case NVPTXISD::StoreV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_avar,
- NVPTX::STV_i16_v4_avar, NVPTX::STV_i32_v4_avar, None,
- NVPTX::STV_f16_v4_avar, NVPTX::STV_f16x2_v4_avar,
- NVPTX::STV_f32_v4_avar, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::STV_i8_v4_avar, NVPTX::STV_i16_v4_avar,
+ NVPTX::STV_i32_v4_avar, std::nullopt,
+ NVPTX::STV_f16_v4_avar, NVPTX::STV_f16x2_v4_avar,
+ NVPTX::STV_f32_v4_avar, std::nullopt);
break;
}
StOps.push_back(Addr);
@@ -1976,11 +1976,11 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
NVPTX::STV_f32_v2_asi, NVPTX::STV_f64_v2_asi);
break;
case NVPTXISD::StoreV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_asi,
- NVPTX::STV_i16_v4_asi, NVPTX::STV_i32_v4_asi, None,
- NVPTX::STV_f16_v4_asi, NVPTX::STV_f16x2_v4_asi,
- NVPTX::STV_f32_v4_asi, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::STV_i8_v4_asi, NVPTX::STV_i16_v4_asi,
+ NVPTX::STV_i32_v4_asi, std::nullopt,
+ NVPTX::STV_f16_v4_asi, NVPTX::STV_f16x2_v4_asi,
+ NVPTX::STV_f32_v4_asi, std::nullopt);
break;
}
StOps.push_back(Base);
@@ -2002,9 +2002,9 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
case NVPTXISD::StoreV4:
Opcode = pickOpcodeForVT(
EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_ari_64,
- NVPTX::STV_i16_v4_ari_64, NVPTX::STV_i32_v4_ari_64, None,
+ NVPTX::STV_i16_v4_ari_64, NVPTX::STV_i32_v4_ari_64, std::nullopt,
NVPTX::STV_f16_v4_ari_64, NVPTX::STV_f16x2_v4_ari_64,
- NVPTX::STV_f32_v4_ari_64, None);
+ NVPTX::STV_f32_v4_ari_64, std::nullopt);
break;
}
} else {
@@ -2019,11 +2019,11 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
NVPTX::STV_f32_v2_ari, NVPTX::STV_f64_v2_ari);
break;
case NVPTXISD::StoreV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_ari,
- NVPTX::STV_i16_v4_ari, NVPTX::STV_i32_v4_ari, None,
- NVPTX::STV_f16_v4_ari, NVPTX::STV_f16x2_v4_ari,
- NVPTX::STV_f32_v4_ari, None);
+ Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy,
+ NVPTX::STV_i8_v4_ari, NVPTX::STV_i16_v4_ari,
+ NVPTX::STV_i32_v4_ari, std::nullopt,
+ NVPTX::STV_f16_v4_ari, NVPTX::STV_f16x2_v4_ari,
+ NVPTX::STV_f32_v4_ari, std::nullopt);
break;
}
}
@@ -2045,9 +2045,9 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
case NVPTXISD::StoreV4:
Opcode = pickOpcodeForVT(
EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg_64,
- NVPTX::STV_i16_v4_areg_64, NVPTX::STV_i32_v4_areg_64, None,
+ NVPTX::STV_i16_v4_areg_64, NVPTX::STV_i32_v4_areg_64, std::nullopt,
NVPTX::STV_f16_v4_areg_64, NVPTX::STV_f16x2_v4_areg_64,
- NVPTX::STV_f32_v4_areg_64, None);
+ NVPTX::STV_f32_v4_areg_64, std::nullopt);
break;
}
} else {
@@ -2063,11 +2063,11 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
NVPTX::STV_f64_v2_areg);
break;
case NVPTXISD::StoreV4:
- Opcode =
- pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg,
- NVPTX::STV_i16_v4_areg, NVPTX::STV_i32_v4_areg, None,
- NVPTX::STV_f16_v4_areg, NVPTX::STV_f16x2_v4_areg,
- NVPTX::STV_f32_v4_areg, None);
+ Opcode = pickOpcodeForVT(
+ EltVT.getSimpleVT().SimpleTy, NVPTX::STV_i8_v4_areg,
+ NVPTX::STV_i16_v4_areg, NVPTX::STV_i32_v4_areg, std::nullopt,
+ NVPTX::STV_f16_v4_areg, NVPTX::STV_f16x2_v4_areg,
+ NVPTX::STV_f32_v4_areg, std::nullopt);
break;
}
}
@@ -2136,9 +2136,9 @@ bool NVPTXDAGToDAGISel::tryLoadParam(SDNode *Node) {
case 4:
Opcode = pickOpcodeForVT(
MemVT.getSimpleVT().SimpleTy, NVPTX::LoadParamMemV4I8,
- NVPTX::LoadParamMemV4I16, NVPTX::LoadParamMemV4I32, None,
+ NVPTX::LoadParamMemV4I16, NVPTX::LoadParamMemV4I32, std::nullopt,
NVPTX::LoadParamMemV4F16, NVPTX::LoadParamMemV4F16x2,
- NVPTX::LoadParamMemV4F32, None);
+ NVPTX::LoadParamMemV4F32, std::nullopt);
break;
}
if (!Opcode)
@@ -2219,9 +2219,9 @@ bool NVPTXDAGToDAGISel::tryStoreRetval(SDNode *N) {
case 4:
Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
NVPTX::StoreRetvalV4I8, NVPTX::StoreRetvalV4I16,
- NVPTX::StoreRetvalV4I32, None,
+ NVPTX::StoreRetvalV4I32, std::nullopt,
NVPTX::StoreRetvalV4F16, NVPTX::StoreRetvalV4F16x2,
- NVPTX::StoreRetvalV4F32, None);
+ NVPTX::StoreRetvalV4F32, std::nullopt);
break;
}
if (!Opcode)
@@ -2298,9 +2298,9 @@ bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
case 4:
Opcode = pickOpcodeForVT(Mem->getMemoryVT().getSimpleVT().SimpleTy,
NVPTX::StoreParamV4I8, NVPTX::StoreParamV4I16,
- NVPTX::StoreParamV4I32, None,
+ NVPTX::StoreParamV4I32, std::nullopt,
NVPTX::StoreParamV4F16, NVPTX::StoreParamV4F16x2,
- NVPTX::StoreParamV4F32, None);
+ NVPTX::StoreParamV4F32, std::nullopt);
break;
}
if (!Opcode)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index ea9f7feaa422f..47c1eae590b2e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -1661,7 +1661,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
- MaybeAlign retAlignment = None;
+ MaybeAlign retAlignment = std::nullopt;
// Handle Result
if (Ins.size() > 0) {
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index 2e678ffd58c2a..ee64bf5addf40 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -268,7 +268,7 @@ Optional<MCFixupKind> ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
if (Type != -1u)
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
- return None;
+ return std::nullopt;
}
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
index eef29d8cc5d52..1f533c105b0ec 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp
@@ -200,7 +200,7 @@ Optional<bool> llvm::isPartOfGOTToPCRelPair(const MCInst &Inst,
const MCSubtargetInfo &STI) {
// Need at least two operands.
if (Inst.getNumOperands() < 2)
- return None;
+ return std::nullopt;
unsigned LastOp = Inst.getNumOperands() - 1;
// The last operand needs to be an MCExpr and it needs to have a variant kind
@@ -208,13 +208,13 @@ Optional<bool> llvm::isPartOfGOTToPCRelPair(const MCInst &Inst,
// link time GOT PC Rel opt instruction and we can ignore it and return None.
const MCOperand &Operand = Inst.getOperand(LastOp);
if (!Operand.isExpr())
- return None;
+ return std::nullopt;
// Check for the variant kind VK_PPC_PCREL_OPT in this expression.
const MCExpr *Expr = Operand.getExpr();
const MCSymbolRefExpr *SymExpr = static_cast<const MCSymbolRefExpr *>(Expr);
if (!SymExpr || SymExpr->getKind() != MCSymbolRefExpr::VK_PPC_PCREL_OPT)
- return None;
+ return std::nullopt;
return (Inst.getOpcode() == PPC::PLDpc);
}
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 5c4bcccb255cc..975dc9a4d4ec4 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -226,7 +226,7 @@ static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
case CmpInst::FCMP_OLE:
case CmpInst::FCMP_ONE:
default:
- return None;
+ return std::nullopt;
case CmpInst::FCMP_OEQ:
case CmpInst::ICMP_EQ:
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 08349dac944c2..5386fd720af11 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -260,7 +260,7 @@ namespace {
/// signed 16-bit immediate.
bool SelectDForm(SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base) {
return PPCLowering->SelectOptimalAddrMode(Parent, N, Disp, Base, *CurDAG,
- None) == PPC::AM_DForm;
+ std::nullopt) == PPC::AM_DForm;
}
/// SelectPCRelForm - Returns true if address N can be represented by
@@ -268,21 +268,22 @@ namespace {
bool SelectPCRelForm(SDNode *Parent, SDValue N, SDValue &Disp,
SDValue &Base) {
return PPCLowering->SelectOptimalAddrMode(Parent, N, Disp, Base, *CurDAG,
- None) == PPC::AM_PCRel;
+ std::nullopt) == PPC::AM_PCRel;
}
/// SelectPDForm - Returns true if address N can be represented by Prefixed
/// DForm addressing mode (a base register, plus a signed 34-bit immediate.
bool SelectPDForm(SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base) {
return PPCLowering->SelectOptimalAddrMode(Parent, N, Disp, Base, *CurDAG,
- None) == PPC::AM_PrefixDForm;
+ std::nullopt) ==
+ PPC::AM_PrefixDForm;
}
/// SelectXForm - Returns true if address N can be represented by the
/// addressing mode of XForm instructions (an indexed [r+r] operation).
bool SelectXForm(SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base) {
return PPCLowering->SelectOptimalAddrMode(Parent, N, Disp, Base, *CurDAG,
- None) == PPC::AM_XForm;
+ std::nullopt) == PPC::AM_XForm;
}
/// SelectForceXForm - Given the specified address, force it to be
@@ -300,7 +301,8 @@ namespace {
/// bit signed displacement.
/// Returns false if it can be represented by [r+imm], which are preferred.
bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
- return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG, None);
+ return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG,
+ std::nullopt);
}
/// SelectAddrIdx4 - Given the specified address, check to see if it can be
@@ -337,7 +339,8 @@ namespace {
/// displacement.
bool SelectAddrImm(SDValue N, SDValue &Disp,
SDValue &Base) {
- return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, None);
+ return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG,
+ std::nullopt);
}
/// SelectAddrImmX4 - Returns true if the address N can be represented by
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 9d5dbffc1aa2c..4ff5154b260cd 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3045,7 +3045,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
// LDU/STU can only handle immediates that are a multiple of 4.
if (VT != MVT::i64) {
- if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
+ if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, std::nullopt))
return false;
} else {
// LDU/STU need an address with at least 4-byte alignment.
@@ -3127,7 +3127,7 @@ SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
SDValue Ops[] = { GA, Reg };
return DAG.getMemIntrinsicNode(
PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
- MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
+ MachinePointerInfo::getGOT(DAG.getMachineFunction()), std::nullopt,
MachineMemOperand::MOLoad);
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 0c5d6940cc988..d46260eda7ace 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -855,7 +855,7 @@ namespace llvm {
/// Returns false if it can be represented by [r+imm], which are preferred.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
SelectionDAG &DAG,
- MaybeAlign EncodingAlignment = None) const;
+ MaybeAlign EncodingAlignment = std::nullopt) const;
/// SelectAddressRegImm - Returns true if the address N can be represented
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
index 9707357e6fd5a..e3fe0ffd2a86d 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
@@ -58,7 +58,7 @@ class FusionFeature {
bool isSupported() const { return Supported; }
std::optional<unsigned> depOpIdx() const {
if (DepOpIdx < 0)
- return None;
+ return std::nullopt;
return DepOpIdx;
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 66f7d80e72ca9..9db903baf4070 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -114,7 +114,7 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
Type *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 9f23cafdd7264..fe2303d06dee3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -41,7 +41,7 @@ Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
if (Type != -1u)
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
- return None;
+ return std::nullopt;
}
const MCFixupKindInfo &
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 44d3b05ceca83..72a7914ef37db 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2183,7 +2183,7 @@ static std::optional<uint64_t> getExactInteger(const APFloat &APF,
if ((APF.convertToInteger(ValInt, ArbitraryRM, &IsExact) ==
APFloatBase::opInvalidOp) ||
!IsExact)
- return None;
+ return std::nullopt;
return ValInt.extractBitsAsZExtValue(BitWidth, 0);
}
@@ -2216,19 +2216,19 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
if (IsInteger) {
// The BUILD_VECTOR must be all constants.
if (!isa<ConstantSDNode>(Op.getOperand(Idx)))
- return None;
+ return std::nullopt;
Val = Op.getConstantOperandVal(Idx) &
maskTrailingOnes<uint64_t>(EltSizeInBits);
} else {
// The BUILD_VECTOR must be all constants.
if (!isa<ConstantFPSDNode>(Op.getOperand(Idx)))
- return None;
+ return std::nullopt;
if (auto ExactInteger = getExactInteger(
cast<ConstantFPSDNode>(Op.getOperand(Idx))->getValueAPF(),
EltSizeInBits))
Val = *ExactInteger;
else
- return None;
+ return std::nullopt;
}
if (PrevElt) {
@@ -2248,7 +2248,7 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
if (Remainder != ValDiff) {
// The
diff erence must cleanly divide the element span.
if (Remainder != 0)
- return None;
+ return std::nullopt;
ValDiff /= IdxDiff;
IdxDiff = 1;
}
@@ -2256,12 +2256,12 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
if (!SeqStepNum)
SeqStepNum = ValDiff;
else if (ValDiff != SeqStepNum)
- return None;
+ return std::nullopt;
if (!SeqStepDenom)
SeqStepDenom = IdxDiff;
else if (IdxDiff != *SeqStepDenom)
- return None;
+ return std::nullopt;
}
// Record this non-undef element for later.
@@ -2271,7 +2271,7 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
// We need to have logged a step for this to count as a legal index sequence.
if (!SeqStepNum || !SeqStepDenom)
- return None;
+ return std::nullopt;
// Loop back through the sequence and validate elements we might have skipped
// while waiting for a valid step. While doing this, log any sequence addend.
@@ -2293,7 +2293,7 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
if (!SeqAddend)
SeqAddend = Addend;
else if (Addend != SeqAddend)
- return None;
+ return std::nullopt;
}
assert(SeqAddend && "Must have an addend if we have a step");
@@ -8843,7 +8843,7 @@ canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS,
bool AllowZExt) {
assert((AllowSExt || AllowZExt) && "Forgot to set what you want?");
if (!LHS.areVLAndMaskCompatible(Root) || !RHS.areVLAndMaskCompatible(Root))
- return None;
+ return std::nullopt;
if (AllowZExt && LHS.SupportsZExt && RHS.SupportsZExt)
return CombineResult(NodeExtensionHelper::getSameExtensionOpcode(
Root->getOpcode(), /*IsSExt=*/false),
@@ -8854,7 +8854,7 @@ canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS,
Root->getOpcode(), /*IsSExt=*/true),
Root, LHS, /*SExtLHS=*/true, RHS,
/*SExtRHS=*/true);
- return None;
+ return std::nullopt;
}
/// Check if \p Root follows a pattern Root(ext(LHS), ext(RHS))
@@ -8878,7 +8878,7 @@ static Optional<CombineResult> canFoldToVW_W(SDNode *Root,
const NodeExtensionHelper &LHS,
const NodeExtensionHelper &RHS) {
if (!RHS.areVLAndMaskCompatible(Root))
- return None;
+ return std::nullopt;
// FIXME: Is it useful to form a vwadd.wx or vwsub.wx if it removes a scalar
// sext/zext?
@@ -8887,12 +8887,12 @@ static Optional<CombineResult> canFoldToVW_W(SDNode *Root,
if (RHS.SupportsZExt && (!RHS.isSplat() || AllowSplatInVW_W))
return CombineResult(
NodeExtensionHelper::getWOpcode(Root->getOpcode(), /*IsSExt=*/false),
- Root, LHS, /*SExtLHS=*/None, RHS, /*SExtRHS=*/false);
+ Root, LHS, /*SExtLHS=*/std::nullopt, RHS, /*SExtRHS=*/false);
if (RHS.SupportsSExt && (!RHS.isSplat() || AllowSplatInVW_W))
return CombineResult(
NodeExtensionHelper::getWOpcode(Root->getOpcode(), /*IsSExt=*/true),
- Root, LHS, /*SExtLHS=*/None, RHS, /*SExtRHS=*/true);
- return None;
+ Root, LHS, /*SExtLHS=*/std::nullopt, RHS, /*SExtRHS=*/true);
+ return std::nullopt;
}
/// Check if \p Root follows a pattern Root(sext(LHS), sext(RHS))
@@ -8925,9 +8925,9 @@ static Optional<CombineResult> canFoldToVW_SU(SDNode *Root,
const NodeExtensionHelper &LHS,
const NodeExtensionHelper &RHS) {
if (!LHS.SupportsSExt || !RHS.SupportsZExt)
- return None;
+ return std::nullopt;
if (!LHS.areVLAndMaskCompatible(Root) || !RHS.areVLAndMaskCompatible(Root))
- return None;
+ return std::nullopt;
return CombineResult(NodeExtensionHelper::getSUOpcode(Root->getOpcode()),
Root, LHS, /*SExtLHS=*/true, RHS, /*SExtRHS=*/false);
}
@@ -11477,7 +11477,7 @@ static Optional<unsigned> preAssignMask(const ArgTy &Args) {
if (ArgVT.isVector() && ArgVT.getVectorElementType() == MVT::i1)
return ArgIdx.index();
}
- return None;
+ return std::nullopt;
}
void RISCVTargetLowering::analyzeInputArgs(
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 9b903462728ad..f03ed1413c860 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -90,7 +90,7 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
static Optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
default:
- return None;
+ return std::nullopt;
case RISCV::VLE8_V:
case RISCV::VLSE8_V:
case RISCV::VSE8_V:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d43bf24129593..582eabdb3cc95 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1124,7 +1124,7 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
break;
}
- return None;
+ return std::nullopt;
}
void RISCVInstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
@@ -2387,7 +2387,7 @@ Optional<std::pair<unsigned, unsigned>>
RISCV::isRVVSpillForZvlsseg(unsigned Opcode) {
switch (Opcode) {
default:
- return None;
+ return std::nullopt;
case RISCV::PseudoVSPILL2_M1:
case RISCV::PseudoVRELOAD2_M1:
return std::make_pair(2u, 1u);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index cfc819ffbf638..794102b512f6a 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -313,7 +313,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
else
DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
- MachineInstr::NoFlags, None);
+ MachineInstr::NoFlags, std::nullopt);
MI.getOperand(FIOperandNum).ChangeToRegister(DestReg, /*IsDef*/false,
/*IsImp*/false,
/*IsKill*/true);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 3710a886ed895..513dc62815c82 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -116,7 +116,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind);
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
index e75acc3441c12..721e659d0a8a4 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -154,7 +154,7 @@ namespace {
.Case("BFD_RELOC_64", ELF::R_SPARC_64)
.Default(-1u);
if (Type == -1u)
- return None;
+ return std::nullopt;
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
index 538380263c3cb..3401c4c708a8a 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
@@ -124,7 +124,7 @@ Optional<MCFixupKind> SystemZMCAsmBackend::getFixupKind(StringRef Name) const {
.Default(-1u);
if (Type != -1u)
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
- return None;
+ return std::nullopt;
}
const MCFixupKindInfo &
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index e0556519bdeda..5d00e56ae3470 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -300,8 +300,8 @@ void SystemZTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
}
if (isa<StoreInst>(&I)) {
Type *MemAccessTy = I.getOperand(0)->getType();
- NumStores += getMemoryOpCost(Instruction::Store, MemAccessTy, None, 0,
- TTI::TCK_RecipThroughput);
+ NumStores += getMemoryOpCost(Instruction::Store, MemAccessTy,
+ std::nullopt, 0, TTI::TCK_RecipThroughput);
}
}
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
index a3f211826d8db..5ac3d8149a1df 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
@@ -93,7 +93,7 @@ class SystemZTTIImpl : public BasicTTIImplBase<SystemZTTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
unsigned getVectorTruncCost(Type *SrcTy, Type *DstTy);
unsigned getVectorBitmaskConversionCost(Type *SrcTy, Type *DstTy);
unsigned getBoolVecToIntConversionCost(unsigned Opcode, Type *Dst,
diff --git a/llvm/lib/Target/VE/VECustomDAG.cpp b/llvm/lib/Target/VE/VECustomDAG.cpp
index 8f11eba6d5fda..6cf5536145ec7 100644
--- a/llvm/lib/Target/VE/VECustomDAG.cpp
+++ b/llvm/lib/Target/VE/VECustomDAG.cpp
@@ -79,7 +79,7 @@ Optional<unsigned> getVVPOpcode(unsigned Opcode) {
case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
return VEISD::VVP_STORE;
}
- return None;
+ return std::nullopt;
}
bool maySafelyIgnoreMask(SDValue Op) {
@@ -185,7 +185,7 @@ Optional<int> getAVLPos(unsigned Opc) {
return 5;
}
- return None;
+ return std::nullopt;
}
Optional<int> getMaskPos(unsigned Opc) {
@@ -208,7 +208,7 @@ Optional<int> getMaskPos(unsigned Opc) {
return 2;
}
- return None;
+ return std::nullopt;
}
bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; }
diff --git a/llvm/lib/Target/VE/VECustomDAG.h b/llvm/lib/Target/VE/VECustomDAG.h
index 0d35c098048ed..f99bffac37eb1 100644
--- a/llvm/lib/Target/VE/VECustomDAG.h
+++ b/llvm/lib/Target/VE/VECustomDAG.h
@@ -154,7 +154,7 @@ class VECustomDAG {
/// getNode {
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef<SDValue> OpV,
- Optional<SDNodeFlags> Flags = None) const {
+ Optional<SDNodeFlags> Flags = std::nullopt) const {
auto N = DAG.getNode(OC, DL, VTL, OpV);
if (Flags)
N->setFlags(*Flags);
@@ -162,7 +162,7 @@ class VECustomDAG {
}
SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
- Optional<SDNodeFlags> Flags = None) const {
+ Optional<SDNodeFlags> Flags = std::nullopt) const {
auto N = DAG.getNode(OC, DL, ResVT, OpV);
if (Flags)
N->setFlags(*Flags);
@@ -170,7 +170,7 @@ class VECustomDAG {
}
SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
- Optional<SDNodeFlags> Flags = None) const {
+ Optional<SDNodeFlags> Flags = std::nullopt) const {
auto N = DAG.getNode(OC, DL, ResVT, OpV);
if (Flags)
N->setFlags(*Flags);
diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp b/llvm/lib/Target/VE/VEFrameLowering.cpp
index 1ae3a2c43f9f1..195bd4e6c3aee 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -357,8 +357,8 @@ void VEFrameLowering::emitPrologue(MachineFunction &MF,
// Emit stack adjust instructions
MaybeAlign RuntimeAlign =
- NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None;
- assert((RuntimeAlign == None || !FuncInfo->isLeafProc()) &&
+ NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : std::nullopt;
+ assert((RuntimeAlign == std::nullopt || !FuncInfo->isLeafProc()) &&
"SP has to be saved in order to align variable sized stack object!");
emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);
@@ -408,7 +408,7 @@ void VEFrameLowering::emitEpilogue(MachineFunction &MF,
.addImm(0);
} else {
// Emit stack adjust instructions.
- emitSPAdjustment(MF, MBB, MBBI, NumBytes, None);
+ emitSPAdjustment(MF, MBB, MBBI, NumBytes, std::nullopt);
}
// Emit Epilogue instructions to restore multiple registers.
diff --git a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
index ae65a9dc2a4ea..87dfeba0648a5 100644
--- a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
+++ b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
@@ -129,21 +129,21 @@ Optional<MCDisassembler::DecodeStatus> WebAssemblyDisassembler::onSymbolStart(
// Start of a code section: we're parsing only the function count.
int64_t FunctionCount;
if (!nextLEB(FunctionCount, Bytes, Size, false))
- return None;
+ return std::nullopt;
outs() << " # " << FunctionCount << " functions in section.";
} else {
// Parse the start of a single function.
int64_t BodySize, LocalEntryCount;
if (!nextLEB(BodySize, Bytes, Size, false) ||
!nextLEB(LocalEntryCount, Bytes, Size, false))
- return None;
+ return std::nullopt;
if (LocalEntryCount) {
outs() << " .local ";
for (int64_t I = 0; I < LocalEntryCount; I++) {
int64_t Count, Type;
if (!nextLEB(Count, Bytes, Size, false) ||
!nextLEB(Type, Bytes, Size, false))
- return None;
+ return std::nullopt;
for (int64_t J = 0; J < Count; J++) {
if (I || J)
outs() << ", ";
diff --git a/llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp b/llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
index d07cf5938d496..579101ffd46cc 100644
--- a/llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
+++ b/llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
@@ -39,7 +39,7 @@ Optional<wasm::ValType> WebAssembly::parseType(StringRef Type) {
return wasm::ValType::FUNCREF;
if (Type == "externref")
return wasm::ValType::EXTERNREF;
- return None;
+ return std::nullopt;
}
WebAssembly::BlockType WebAssembly::parseBlockType(StringRef Type) {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
index f73b781de8a58..40a4b7dbd862b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
@@ -63,7 +63,7 @@ WebAssemblyFrameLowering::getLocalForStackObject(MachineFunction &MF,
// linear memory.
const AllocaInst *AI = MFI.getObjectAllocation(FrameIndex);
if (!AI || !WebAssembly::isWasmVarAddressSpace(AI->getAddressSpace()))
- return None;
+ return std::nullopt;
// Otherwise, allocate this object in the named value stack, outside of linear
// memory.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index b554acc898110..2751be219474e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1452,7 +1452,7 @@ static bool IsWebAssemblyGlobal(SDValue Op) {
static Optional<unsigned> IsWebAssemblyLocal(SDValue Op, SelectionDAG &DAG) {
const FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op);
if (!FI)
- return None;
+ return std::nullopt;
auto &MF = DAG.getMachineFunction();
return WebAssemblyFrameLowering::getLocalForStackObject(MF, FI->getIndex());
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
index 63397a218a29d..7eca7d9ea870b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
@@ -773,7 +773,7 @@ void WebAssemblyLowerEmscriptenEHSjLj::wrapTestSetjmp(
// Output parameter assignment
Label = LabelPHI;
EndBB = EndBB1;
- LongjmpResult = IRB.CreateCall(GetTempRet0F, None, "longjmp_result");
+ LongjmpResult = IRB.CreateCall(GetTempRet0F, std::nullopt, "longjmp_result");
}
void WebAssemblyLowerEmscriptenEHSjLj::rebuildSSA(Function &F) {
@@ -1227,7 +1227,7 @@ bool WebAssemblyLowerEmscriptenEHSjLj::runEHOnFunction(Function &F) {
CallInst *FMCI = IRB.CreateCall(FMCF, FMCArgs, "fmc");
Value *Poison = PoisonValue::get(LPI->getType());
Value *Pair0 = IRB.CreateInsertValue(Poison, FMCI, 0, "pair0");
- Value *TempRet0 = IRB.CreateCall(GetTempRet0F, None, "tempret0");
+ Value *TempRet0 = IRB.CreateCall(GetTempRet0F, std::nullopt, "tempret0");
Value *Pair1 = IRB.CreateInsertValue(Pair0, TempRet0, 1, "pair1");
LPI->replaceAllUsesWith(Pair1);
@@ -1355,7 +1355,7 @@ bool WebAssemblyLowerEmscriptenEHSjLj::runSjLjOnFunction(Function &F) {
Instruction *NewSetjmpTable =
IRB.CreateCall(SaveSetjmpF, Args, "setjmpTable");
Instruction *NewSetjmpTableSize =
- IRB.CreateCall(GetTempRet0F, None, "setjmpTableSize");
+ IRB.CreateCall(GetTempRet0F, std::nullopt, "setjmpTableSize");
SetjmpTableInsts.push_back(NewSetjmpTable);
SetjmpTableSizeInsts.push_back(NewSetjmpTableSize);
ToErase.push_back(CI);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index f667e040ea086..bdf242a37df59 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1078,7 +1078,7 @@ class X86AsmParser : public MCTargetAsmParser {
void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
};
- bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
+ bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt,
bool MatchingInlineAsm = false) {
MCAsmParser &Parser = getParser();
if (MatchingInlineAsm) {
@@ -4137,7 +4137,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
bool MatchingInlineAsm) {
assert(!Operands.empty() && "Unexpect empty operand list!");
assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
- SMRange EmptyRange = None;
+ SMRange EmptyRange = std::nullopt;
// First, handle aliases that expand to multiple instructions.
MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands,
@@ -4396,7 +4396,7 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
assert(!Operands.empty() && "Unexpect empty operand list!");
assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
- SMRange EmptyRange = None;
+ SMRange EmptyRange = std::nullopt;
StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
unsigned Prefixes = getPrefixes(Operands);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index a5d11ccf89ce4..f8b0471300fb5 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -613,7 +613,7 @@ Optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
.Default(-1u);
}
if (Type == -1u)
- return None;
+ return std::nullopt;
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
}
return MCAsmBackend::getFixupKind(Name);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index dcfbd305b732c..12d9acc1ebead 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -643,7 +643,7 @@ Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
if (MemOpStart == -1)
- return None;
+ return std::nullopt;
MemOpStart += X86II::getOperandBias(MCID);
const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
@@ -653,24 +653,24 @@ Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 ||
!Disp.isImm())
- return None;
+ return std::nullopt;
// RIP-relative addressing.
if (BaseReg.getReg() == X86::RIP)
return Addr + Size + Disp.getImm();
- return None;
+ return std::nullopt;
}
Optional<uint64_t>
X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
uint64_t Size) const {
if (Inst.getOpcode() != X86::LEA64r)
- return None;
+ return std::nullopt;
const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags);
if (MemOpStart == -1)
- return None;
+ return std::nullopt;
MemOpStart += X86II::getOperandBias(MCID);
const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
@@ -680,7 +680,7 @@ X86MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst,
// Must be a simple rip-relative address.
if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 ||
IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm())
- return None;
+ return std::nullopt;
// rip-relative ModR/M immediate is 32 bits.
assert(Size > 4 && "invalid instruction size for rip-relative lea");
return Size - 4;
diff --git a/llvm/lib/Target/X86/X86FrameLowering.h b/llvm/lib/Target/X86/X86FrameLowering.h
index 9b83fe77d5059..bc209fa9e9136 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.h
+++ b/llvm/lib/Target/X86/X86FrameLowering.h
@@ -54,10 +54,11 @@ class X86FrameLowering : public TargetFrameLowering {
/// the number of bytes to probe in RAX/EAX.
/// \p InstrNum optionally contains a debug-info instruction number for the
/// new stack pointer.
- void emitStackProbe(
- MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog,
- Optional<MachineFunction::DebugInstrOperandPair> InstrNum = None) const;
+ void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
+ bool InProlog,
+ Optional<MachineFunction::DebugInstrOperandPair>
+ InstrNum = std::nullopt) const;
bool stackProbeFunctionModifiesSP() const override;
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index c8bc586c18b00..6249276adfa45 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -449,8 +449,8 @@ namespace {
// Create zero.
SDVTList VTs = CurDAG->getVTList(MVT::i32, MVT::i32);
- SDValue Zero =
- SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, VTs, None), 0);
+ SDValue Zero = SDValue(
+ CurDAG->getMachineNode(X86::MOV32r0, dl, VTs, std::nullopt), 0);
if (VT == MVT::i64) {
Zero = SDValue(
CurDAG->getMachineNode(
@@ -1375,7 +1375,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
SDVTList VTs = CurDAG->getVTList(MVT::Other);
SDValue Ops[] = {N->getOperand(0), N->getOperand(1), MemTmp};
Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT,
- MPI, /*Align*/ None,
+ MPI, /*Align*/ std::nullopt,
MachineMemOperand::MOStore);
if (N->getFlags().hasNoFPExcept()) {
SDNodeFlags Flags = Store->getFlags();
@@ -1393,7 +1393,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
SDValue Ops[] = {Store, MemTmp};
Result = CurDAG->getMemIntrinsicNode(
X86ISD::FLD, dl, VTs, Ops, MemVT, MPI,
- /*Align*/ None, MachineMemOperand::MOLoad);
+ /*Align*/ std::nullopt, MachineMemOperand::MOLoad);
if (N->getFlags().hasNoFPExcept()) {
SDNodeFlags Flags = Result->getFlags();
Flags.setNoFPExcept(true);
@@ -3505,11 +3505,11 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
Op.getNode()->hasNUsesOfValue(NUses, Op.getResNo());
};
auto checkOneUse = [checkUses](SDValue Op,
- Optional<bool> AllowExtraUses = None) {
+ Optional<bool> AllowExtraUses = std::nullopt) {
return checkUses(Op, 1, AllowExtraUses);
};
auto checkTwoUse = [checkUses](SDValue Op,
- Optional<bool> AllowExtraUses = None) {
+ Optional<bool> AllowExtraUses = std::nullopt) {
return checkUses(Op, 2, AllowExtraUses);
};
@@ -5411,8 +5411,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
} else {
// Zero out the high part, effectively zero extending the input.
SDVTList VTs = CurDAG->getVTList(MVT::i32, MVT::i32);
- SDValue ClrNode =
- SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, VTs, None), 0);
+ SDValue ClrNode = SDValue(
+ CurDAG->getMachineNode(X86::MOV32r0, dl, VTs, std::nullopt), 0);
switch (NVT.SimpleTy) {
case MVT::i16:
ClrNode =
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f445550d4f295..ef5a72d4c8230 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3815,14 +3815,14 @@ static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
// in their paired GPR. So we only need to save the GPR to their home
// slots.
// TODO: __vectorcall will change this.
- return None;
+ return std::nullopt;
}
bool isSoftFloat = Subtarget.useSoftFloat();
if (isSoftFloat || !Subtarget.hasSSE1())
// Kernel mode asks for SSE to be disabled, so there are no XMM argument
// registers.
- return None;
+ return std::nullopt;
static const MCPhysReg XMMArgRegs64Bit[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
@@ -22990,13 +22990,14 @@ SDValue X86TargetLowering::LRINT_LLRINTHelper(SDNode *N,
SDValue Ops[] = { Chain, StackPtr };
Src = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, SrcVT, MPI,
- /*Align*/ None, MachineMemOperand::MOLoad);
+ /*Align*/ std::nullopt,
+ MachineMemOperand::MOLoad);
Chain = Src.getValue(1);
}
SDValue StoreOps[] = { Chain, Src, StackPtr };
Chain = DAG.getMemIntrinsicNode(X86ISD::FIST, DL, DAG.getVTList(MVT::Other),
- StoreOps, DstVT, MPI, /*Align*/ None,
+ StoreOps, DstVT, MPI, /*Align*/ std::nullopt,
MachineMemOperand::MOStore);
return DAG.getLoad(DstVT, DL, Chain, StackPtr, MPI);
@@ -26453,7 +26454,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
SDValue VAARG = DAG.getMemIntrinsicNode(
Subtarget.isTarget64BitLP64() ? X86ISD::VAARG_64 : X86ISD::VAARG_X32, dl,
VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
- /*Alignment=*/None,
+ /*Alignment=*/std::nullopt,
MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
Chain = VAARG.getValue(1);
@@ -32353,9 +32354,9 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG,
MPI, MaybeAlign(), MachineMemOperand::MOStore);
SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
SDValue LdOps[] = {Chain, StackPtr};
- SDValue Value =
- DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, LdOps, MVT::i64, MPI,
- /*Align*/ None, MachineMemOperand::MOLoad);
+ SDValue Value = DAG.getMemIntrinsicNode(
+ X86ISD::FILD, dl, Tys, LdOps, MVT::i64, MPI,
+ /*Align*/ std::nullopt, MachineMemOperand::MOLoad);
Chain = Value.getValue(1);
// Now use an FIST to do the atomic store.
@@ -33939,7 +33940,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
SDValue StoreOps[] = { Chain, Result, StackPtr };
Chain = DAG.getMemIntrinsicNode(
X86ISD::FIST, dl, DAG.getVTList(MVT::Other), StoreOps, MVT::i64,
- MPI, None /*Align*/, MachineMemOperand::MOStore);
+ MPI, std::nullopt /*Align*/, MachineMemOperand::MOStore);
// Finally load the value back from the stack temporary and return it.
// This load is not atomic and doesn't need to be.
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index ea34f45173ce9..6c932a58ac154 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3577,7 +3577,7 @@ Optional<DestSourcePair>
X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
if (MI.isMoveReg())
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
- return None;
+ return std::nullopt;
}
static unsigned getLoadStoreOpcodeForFP16(bool Load, const X86Subtarget &STI) {
@@ -3734,18 +3734,18 @@ X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
const MCInstrDesc &Desc = MemI.getDesc();
int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
if (MemRefBegin < 0)
- return None;
+ return std::nullopt;
MemRefBegin += X86II::getOperandBias(Desc);
auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
if (!BaseOp.isReg()) // Can be an MO_FrameIndex
- return None;
+ return std::nullopt;
const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
// Displacement can be symbolic
if (!DispMO.isImm())
- return None;
+ return std::nullopt;
ExtAddrMode AM;
AM.BaseReg = BaseOp.getReg();
@@ -9068,7 +9068,7 @@ describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
// possible.
if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
!TRI->isSuperRegister(DestReg, DescribedReg))
- return None;
+ return std::nullopt;
assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
@@ -9087,12 +9087,12 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
case X86::LEA64_32r: {
// We may need to describe a 64-bit parameter with a 32-bit LEA.
if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
- return None;
+ return std::nullopt;
// Operand 4 could be global address. For now we do not support
// such situation.
if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
- return None;
+ return std::nullopt;
const MachineOperand &Op1 = MI.getOperand(1);
const MachineOperand &Op2 = MI.getOperand(3);
@@ -9103,12 +9103,12 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
// %rsi = lea %rsi, 4, ...
if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
Op2.getReg() == MI.getOperand(0).getReg())
- return None;
+ return std::nullopt;
else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
(Op2.getReg() != X86::NoRegister &&
TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
- return None;
+ return std::nullopt;
int64_t Coef = MI.getOperand(2).getImm();
int64_t Offset = MI.getOperand(4).getImm();
@@ -9127,7 +9127,7 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
if (Op && Op2.getReg() != X86::NoRegister) {
int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
if (dwarfReg < 0)
- return None;
+ return std::nullopt;
else if (dwarfReg < 32) {
Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
Ops.push_back(0);
@@ -9162,14 +9162,14 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
case X86::MOV8ri:
case X86::MOV16ri:
// TODO: Handle MOV8ri and MOV16ri.
- return None;
+ return std::nullopt;
case X86::MOV32ri:
case X86::MOV64ri:
case X86::MOV64ri32:
// MOV32ri may be used for producing zero-extended 32-bit immediates in
// 64-bit parameters, so we need to consider super-registers.
if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
- return None;
+ return std::nullopt;
return ParamLoadedValue(MI.getOperand(1), Expr);
case X86::MOV8rr:
case X86::MOV16rr:
@@ -9180,10 +9180,10 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
// 64-bit parameters are zero-materialized using XOR32rr, so also consider
// super-registers.
if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
- return None;
+ return std::nullopt;
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
- return None;
+ return std::nullopt;
}
case X86::MOVSX64rr32: {
// We may need to describe the lower 32 bits of the MOVSX; for example, in
@@ -9193,7 +9193,7 @@ X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
// $rdi = MOVSX64rr32 $ebx
// $esi = MOV32rr $edi
if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
- return None;
+ return std::nullopt;
Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
diff --git a/llvm/lib/Target/X86/X86LowerAMXType.cpp b/llvm/lib/Target/X86/X86LowerAMXType.cpp
index 7e7577e624f7c..325bc3af83e84 100644
--- a/llvm/lib/Target/X86/X86LowerAMXType.cpp
+++ b/llvm/lib/Target/X86/X86LowerAMXType.cpp
@@ -246,8 +246,8 @@ void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) {
Builder.CreateBitCast(LD->getOperand(0), Builder.getInt8PtrTy());
std::array<Value *, 4> Args = {Row, Col, I8Ptr, Stride};
- Value *NewInst =
- Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal, None, Args);
+ Value *NewInst = Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal,
+ std::nullopt, Args);
Bitcast->replaceAllUsesWith(NewInst);
}
@@ -273,7 +273,8 @@ void X86LowerAMXType::combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST) {
Value *I8Ptr =
Builder.CreateBitCast(ST->getOperand(1), Builder.getInt8PtrTy());
std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Tile};
- Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, None, Args);
+ Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, std::nullopt,
+ Args);
if (Bitcast->hasOneUse())
return;
// %13 = bitcast x86_amx %src to <256 x i32>
@@ -323,7 +324,7 @@ bool X86LowerAMXType::transformBitcast(BitCastInst *Bitcast) {
std::tie(Row, Col) = getShape(II, OpNo);
std::array<Value *, 4> Args = {Row, Col, I8Ptr, Stride};
Value *NewInst = Builder.CreateIntrinsic(
- Intrinsic::x86_tileloadd64_internal, None, Args);
+ Intrinsic::x86_tileloadd64_internal, std::nullopt, Args);
Bitcast->replaceAllUsesWith(NewInst);
} else {
// %2 = bitcast x86_amx %src to <256 x i32>
@@ -340,7 +341,8 @@ bool X86LowerAMXType::transformBitcast(BitCastInst *Bitcast) {
Value *Row = II->getOperand(0);
Value *Col = II->getOperand(1);
std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Src};
- Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, None, Args);
+ Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, std::nullopt,
+ Args);
Value *NewInst = Builder.CreateLoad(Bitcast->getType(), AllocaAddr);
Bitcast->replaceAllUsesWith(NewInst);
}
@@ -472,8 +474,8 @@ static Instruction *createTileStore(Instruction *TileDef, Value *Ptr) {
Value *Stride = Builder.getInt64(64);
std::array<Value *, 5> Args = {Row, Col, Ptr, Stride, TileDef};
- Instruction *TileStore =
- Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, None, Args);
+ Instruction *TileStore = Builder.CreateIntrinsic(
+ Intrinsic::x86_tilestored64_internal, std::nullopt, Args);
return TileStore;
}
@@ -497,8 +499,8 @@ static void replaceWithTileLoad(Use &U, Value *Ptr, bool IsPHI = false) {
Value *Stride = Builder.getInt64(64);
std::array<Value *, 4> Args = {Row, Col, Ptr, Stride};
- Value *TileLoad =
- Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal, None, Args);
+ Value *TileLoad = Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal,
+ std::nullopt, Args);
UserI->replaceUsesOfWith(V, TileLoad);
}
@@ -791,7 +793,7 @@ bool X86LowerAMXCast::optimizeAMXCastFromPhi(
auto *Block = OldPN->getIncomingBlock(I);
BasicBlock::iterator Iter = Block->getTerminator()->getIterator();
Instruction *NewInst = Builder.CreateIntrinsic(
- Intrinsic::x86_tilezero_internal, None, {Row, Col});
+ Intrinsic::x86_tilezero_internal, std::nullopt, {Row, Col});
NewInst->moveBefore(&*Iter);
NewInst = Builder.CreateIntrinsic(Intrinsic::x86_cast_tile_to_vector,
{IncValue->getType()}, {NewInst});
@@ -936,7 +938,8 @@ void X86LowerAMXCast::combineCastStore(IntrinsicInst *Cast, StoreInst *ST) {
Value *I8Ptr =
Builder.CreateBitCast(ST->getOperand(1), Builder.getInt8PtrTy());
std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Tile};
- Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, None, Args);
+ Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, std::nullopt,
+ Args);
}
// %65 = load <256 x i32>, <256 x i32>* %p, align 64
@@ -979,8 +982,8 @@ bool X86LowerAMXCast::combineLoadCast(IntrinsicInst *Cast, LoadInst *LD) {
}
std::array<Value *, 4> Args = {Row, Col, I8Ptr, Stride};
- Value *NewInst =
- Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal, None, Args);
+ Value *NewInst = Builder.CreateIntrinsic(Intrinsic::x86_tileloadd64_internal,
+ std::nullopt, Args);
Cast->replaceAllUsesWith(NewInst);
return EraseLoad;
@@ -1158,7 +1161,7 @@ bool X86LowerAMXCast::transformAMXCast(IntrinsicInst *AMXCast) {
std::array<Value *, 4> Args = {
Row, Col, I8Ptr, Builder.CreateSExt(Col, Builder.getInt64Ty())};
Value *NewInst = Builder.CreateIntrinsic(
- Intrinsic::x86_tileloadd64_internal, None, Args);
+ Intrinsic::x86_tileloadd64_internal, std::nullopt, Args);
AMXCast->replaceAllUsesWith(NewInst);
AMXCast->eraseFromParent();
} else {
@@ -1177,7 +1180,8 @@ bool X86LowerAMXCast::transformAMXCast(IntrinsicInst *AMXCast) {
Value *Col = II->getOperand(1);
std::array<Value *, 5> Args = {
Row, Col, I8Ptr, Builder.CreateSExt(Col, Builder.getInt64Ty()), Src};
- Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, None, Args);
+ Builder.CreateIntrinsic(Intrinsic::x86_tilestored64_internal, std::nullopt,
+ Args);
Value *NewInst = Builder.CreateLoad(AMXCast->getType(), AllocaAddr);
AMXCast->replaceAllUsesWith(NewInst);
AMXCast->eraseFromParent();
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index feac636d96aa3..73cc632c970b1 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -438,7 +438,7 @@ X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit())
- return None;
+ return std::nullopt;
return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
return MCOperand::createImm(MO.getImm());
@@ -457,7 +457,7 @@ X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
case MachineOperand::MO_RegisterMask:
// Ignore call clobbers.
- return None;
+ return std::nullopt;
}
}
diff --git a/llvm/lib/Target/X86/X86PreAMXConfig.cpp b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
index cd0d448238a6e..2429b85cf868e 100644
--- a/llvm/lib/Target/X86/X86PreAMXConfig.cpp
+++ b/llvm/lib/Target/X86/X86PreAMXConfig.cpp
@@ -199,7 +199,8 @@ void X86PreAMXConfig::addTileConfig(Instruction *ModelStart,
preWriteTileCfg(I8Ptr, Builder, Shapes);
- Builder.CreateIntrinsic(Intrinsic::x86_ldtilecfg_internal, None, {I8Ptr});
+ Builder.CreateIntrinsic(Intrinsic::x86_ldtilecfg_internal, std::nullopt,
+ {I8Ptr});
}
// Todo: We may need to handle "more than one store" case in the future.
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index a5f2b9786e8a2..a730d9470aed2 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1489,8 +1489,8 @@ InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
SubLT.second.getVectorNumElements());
int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
InstructionCost ExtractCost =
- getShuffleCost(TTI::SK_ExtractSubvector, VecTy, None, CostKind,
- ExtractIndex, SubTy);
+ getShuffleCost(TTI::SK_ExtractSubvector, VecTy, std::nullopt,
+ CostKind, ExtractIndex, SubTy);
// If the original size is 32-bits or more, we can use pshufd. Otherwise
// if we have SSSE3 we can use pshufb.
@@ -1642,7 +1642,7 @@ InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy,
- None, CostKind, 0, nullptr);
+ std::nullopt, CostKind, 0, nullptr);
}
return BaseT::getShuffleCost(Kind, BaseTp, Mask, CostKind, Index, SubTp);
@@ -4369,8 +4369,8 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
EVT VT = TLI->getValueType(DL, Val);
if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128)
SubTy = FixedVectorType::get(ScalarType, SubNumElts);
- ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, CostKind,
- 0, SubTy);
+ ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, std::nullopt,
+ CostKind, 0, SubTy);
}
int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1;
return ShuffleCost + IntOrFpCost + RegisterFileMoveCost;
@@ -4453,8 +4453,8 @@ InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
// FIXME: we don't need to extract if all non-demanded elements
// are legalization-inserted padding.
if (!LaneEltMask.isAllOnes())
- Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, CostKind,
- I * NumEltsPerLane, LaneTy);
+ Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
+ CostKind, I * NumEltsPerLane, LaneTy);
Cost += BaseT::getScalarizationOverhead(LaneTy, LaneEltMask, Insert,
false);
}
@@ -4471,8 +4471,8 @@ InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
if (!AffectedLanes[I] ||
(Lane == 0 && FullyAffectedLegalVectors[LegalVec]))
continue;
- Cost += getShuffleCost(TTI::SK_InsertSubvector, Ty, None, CostKind,
- I * NumEltsPerLane, LaneTy);
+ Cost += getShuffleCost(TTI::SK_InsertSubvector, Ty, std::nullopt,
+ CostKind, I * NumEltsPerLane, LaneTy);
}
}
}
@@ -4531,8 +4531,8 @@ InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
NumEltsPerLane, I * NumEltsPerLane);
if (LaneEltMask.isNullValue())
continue;
- Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, CostKind,
- I * NumEltsPerLane, LaneTy);
+ Cost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
+ CostKind, I * NumEltsPerLane, LaneTy);
Cost += BaseT::getScalarizationOverhead(LaneTy, LaneEltMask, false,
Extract);
}
@@ -4651,9 +4651,9 @@ X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation();
- InstructionCost SingleShuffleCost =
- getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/None,
- CostKind, /*Index=*/0, /*SubTp=*/nullptr);
+ InstructionCost SingleShuffleCost = getShuffleCost(
+ TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/std::nullopt, CostKind,
+ /*Index=*/0, /*SubTp=*/nullptr);
return NumDstVectorsDemanded * SingleShuffleCost;
}
@@ -4780,7 +4780,8 @@ InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
if (!Is0thSubVec)
Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector
: TTI::ShuffleKind::SK_ExtractSubvector,
- VTy, None, CostKind, NumEltDone(), CurrVecTy);
+ VTy, std::nullopt, CostKind, NumEltDone(),
+ CurrVecTy);
}
// While we can directly load/store ZMM, YMM, and 64-bit halves of XMM,
@@ -4859,17 +4860,17 @@ X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment,
if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
LT.second.getVectorNumElements() == NumElem)
// Promotion requires extend/truncate for data and a shuffle for mask.
- Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, CostKind, 0,
- nullptr) +
- getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, CostKind, 0,
- nullptr);
+ Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, std::nullopt,
+ CostKind, 0, nullptr) +
+ getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, std::nullopt,
+ CostKind, 0, nullptr);
else if (LT.first * LT.second.getVectorNumElements() > NumElem) {
auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(),
LT.second.getVectorNumElements());
// Expanding requires fill mask with zeroes
- Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, CostKind,
- 0, MaskTy);
+ Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, std::nullopt,
+ CostKind, 0, MaskTy);
}
// Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
@@ -5114,8 +5115,9 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
// If we're reducing from 256/512 bits, use an extract_subvector.
if (Size > 128) {
auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
- ReductionCost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, None,
- CostKind, NumVecElts, SubTy);
+ ReductionCost +=
+ getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt, CostKind,
+ NumVecElts, SubTy);
Ty = SubTy;
} else if (Size == 128) {
// Reducing from 128 bits is a permute of v2f64/v2i64.
@@ -5127,7 +5129,7 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
ShufTy =
FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2);
ReductionCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
- None, CostKind, 0, nullptr);
+ std::nullopt, CostKind, 0, nullptr);
} else if (Size == 64) {
// Reducing from 64 bits is a shuffle of v4f32/v4i32.
FixedVectorType *ShufTy;
@@ -5138,7 +5140,7 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
ShufTy =
FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4);
ReductionCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
- None, CostKind, 0, nullptr);
+ std::nullopt, CostKind, 0, nullptr);
} else {
// Reducing from smaller size is a shift by immediate.
auto *ShiftTy = FixedVectorType::get(
@@ -5415,8 +5417,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
// If we're reducing from 256/512 bits, use an extract_subvector.
if (Size > 128) {
auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
- MinMaxCost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, CostKind,
- NumVecElts, SubTy);
+ MinMaxCost += getShuffleCost(TTI::SK_ExtractSubvector, Ty, std::nullopt,
+ CostKind, NumVecElts, SubTy);
Ty = SubTy;
} else if (Size == 128) {
// Reducing from 128 bits is a permute of v2f64/v2i64.
@@ -5426,8 +5428,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2);
else
ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2);
- MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None,
- CostKind, 0, nullptr);
+ MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
+ std::nullopt, CostKind, 0, nullptr);
} else if (Size == 64) {
// Reducing from 64 bits is a shuffle of v4f32/v4i32.
FixedVectorType *ShufTy;
@@ -5435,8 +5437,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4);
else
ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4);
- MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None,
- CostKind, 0, nullptr);
+ MinMaxCost += getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy,
+ std::nullopt, CostKind, 0, nullptr);
} else {
// Reducing from smaller size is a shift by immediate.
auto *ShiftTy = FixedVectorType::get(
@@ -6239,8 +6241,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512(
TTI::ShuffleKind ShuffleKind =
(NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
- InstructionCost ShuffleCost =
- getShuffleCost(ShuffleKind, SingleMemOpTy, None, CostKind, 0, nullptr);
+ InstructionCost ShuffleCost = getShuffleCost(
+ ShuffleKind, SingleMemOpTy, std::nullopt, CostKind, 0, nullptr);
unsigned NumOfLoadsInInterleaveGrp =
Indices.size() ? Indices.size() : Factor;
@@ -6297,7 +6299,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512(
// shuffle.
unsigned NumOfSources = Factor; // The number of values to be merged.
InstructionCost ShuffleCost = getShuffleCost(
- TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, CostKind, 0, nullptr);
+ TTI::SK_PermuteTwoSrc, SingleMemOpTy, std::nullopt, CostKind, 0, nullptr);
unsigned NumOfShufflesPerStore = NumOfSources - 1;
// The SK_MergeTwoSrc shuffle clobbers one of src operands.
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h
index 6ea644f1ecc38..666789e160dca 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.h
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h
@@ -137,7 +137,7 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
- ArrayRef<const Value *> Args = None);
+ ArrayRef<const Value *> Args = std::nullopt);
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
TTI::CastContextHint CCH,
TTI::TargetCostKind CostKind,
More information about the llvm-commits
mailing list