[PATCH] D136722: [AArch64] Extending lowering of 'zext <Y x i8> %x to <Y x i8X>' to use tbl instructions

[NILANJANA BASU via Phabricator via llvm-commits]

nilanjana_basu added a comment.

Removed tbl-conversion cases to destination vector element width above 64, due to observed performance regressions. Will move this to a later patch, once we find a fix.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136722/new/

https://reviews.llvm.org/D136722